TC4015BDR2, TC4015BFN, TC4015BP Selling Leads, Datasheet
MFG:TOS Package Cooled:92+/95+ D/C:01+
TC4015BDR2, TC4015BFN, TC4015BP Datasheet download

Part Number: TC4015BDR2
MFG: TOS
Package Cooled: 92+/95+
D/C: 01+
MFG:TOS Package Cooled:92+/95+ D/C:01+
TC4015BDR2, TC4015BFN, TC4015BP Datasheet download

MFG: TOS
Package Cooled: 92+/95+
D/C: 01+
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PDF/DataSheet Download
Datasheet: TC4001
File Size: 197001 KB
Manufacturer: TOSHIBA [Toshiba Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TC4015BFN
File Size: 268678 KB
Manufacturer: TOSHIBA [Toshiba Semiconductor]
Download : Click here to Download
PDF/DataSheet Download
Datasheet: TC4015BP
File Size: 268678 KB
Manufacturer: TOSHIBA [Toshiba Semiconductor]
Download : Click here to Download
TC4015B contains two circuits of 4 stage shift registers and the independent output is drived from each stage. As all the D type flip-flops of every stage have common RESET input, asynchronous clear operation can be achieved by an external signal at arbitrary timing. The flip-flop of each stage is triggered by rising edge of CLOCK input.
RESET input of "H" level resets the contents of all the stages to "L" regardless of CLOCK and DATA inputs and all of data outputs Q1 through Q4 become "L".
This can be used for converting serial data to palallel one and for ring counters of any numbering systems.
|
Characteristics |
Symbol |
Rating |
Unit |
| DC supply voltage |
VDD |
VSS − 0.5~VSS + 20 |
V |
| Input voltage |
VIN |
VSS − 0.5~VDD + 0.5 |
V |
| Output voltage |
VOUT |
VSS − 0.5~VDD + 0.5 |
V |
| DC input current |
IIN |
±10 |
mA |
| Power Dissipation |
PD |
300 (DIP)/180 (SOIC) |
mW |
| Operating temperature range |
Topr |
−40~85 |
|
| Storage Temperature range |
TSTG |
−65~150 |

TC4015B contains two circuits of 4 stage shift registers and the independent output is drived from each stage. As all the D type flip-flops of every stage have common RESET input, asynchronous clear operation can be achieved by an external signal at arbitrary timing. The flip-flop of each stage is triggered by rising edge of CLOCK input.
RESET input of "H" level resets the contents of all the stages to "L" regardless of CLOCK and DATA inputs and all of data outputs Q1 through Q4 become "L".
This can be used for converting serial data to palallel one and for ring counters of any numbering systems.
|
Characteristics |
Symbol |
Rating |
Unit |
| DC supply voltage |
VDD |
VSS − 0.5~VSS + 20 |
V |
| Input voltage |
VIN |
VSS − 0.5~VDD + 0.5 |
V |
| Output voltage |
VOUT |
VSS − 0.5~VDD + 0.5 |
V |
| DC input current |
IIN |
±10 |
mA |
| Power Dissipation |
PD |
300 (DIP)/180 (SOIC) |
mW |
| Operating temperature range |
Topr |
−40~85 |
|
| Storage Temperature range |
TSTG |
−65~150 |

