TLK2201JR, TLK2201RCP, TLK2208A

The TLK2201JR is a member of the transceiver family of multigigabit transceivers, optimized for use with small form-factor optical transceivers that require footprints smaller than 14 mm. The TLK2201JR gigabit ethernet transceiver is fully compliant with IEEE 802.3 requirements for serializer/deserializer functions at 1.25 Gbps. The TLK2201JR supports a wide range of serial data rates from 1.0 Gbps to 1.6 Gbps.

The primary application of this device is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 or 75 . The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2201JR performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1.0 Gbps of data bandwidth over a copper or optical media interface.

The TLK2201JR supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface with double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (serdes) accepts 10-bit wide 8-bit/10-bit (8b/10b) parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The serdes extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.

In the DDR mode the parallel interface accepts 5-bit wide 8-bit/10-bit encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first (i.e., bits 04 of the 8-bit/10-bit encoded data) on the rising edge of the clock, and the least significant bits (i.e., bits 59 of the 8-bit/10-bit encoded data) are clocked on the falling edge of the clock.

The transceiver automatically locks onto incoming data without the need to prelock.

The TLK2201JR provides a comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported.

The TLK2201JR is housed in a high-performance, thermally enhanced, 80-pin land grid array (LGA) MicroStarJr package. Use of the MicroStarJr package does not require any special considerations. All ac performance specifications in this data sheet are measured with the MicroStarJr soldered to the test board.

The TLK2201JR is characterized for operation from 0°C to 70°C.

The TLK2201JR uses a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply the chipset is very power efficient dissipating less than 250 mW typical power when operating at 1.25 Gbps.

The TLK2201JR is designed to be hot plug capable. A power-on reset holds RCB0 and RCB1 low. The parallel side output pins, TXP and TXN go to high-impedance during power up.

The TLK2208A is the third generation of Gigabit Ethernet transceivers from Texas Instruments combining high port density and ultralow power in a small form-factor footprint. The TLK2208A provides for high-speed full-duplex point-to-point data transmissions based on the IEEE 802.3z 1000-Mbps Ethernet specification. The TLK2208A supports data rates from 1.0 Gbps through 1.3 Gbps.

The primary application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled impedance media of 50 . The transmission media can be printed circuit board traces, copper cables or fiber-optical interface modules. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK2208A performs the data encoding, decoding, serialization, deserialization, clock extraction, and clock tolerance compensation functions for a physical layer interface device. Each channel operates at up to 1.3 Gbps providing up to 8.32 Gbps of aggregate data bandwidth over copper or optical-media interfaces.

The TLK2208A supports two selectable reduced-pin-count double-data-rate (DDR) timing interfaces, nibble mode and multiplexed channel mode, to a protocol device.

In the nibble interface mode, the parallel interface accepts nibble-wide unencoded or 8b/10b encoded data aligned to both the rising and falling edges of the transmit clock.

In the multiplexed channel mode, the parallel interface accepts 8-bit-wide unencoded or 10-bit-wide 8b/10b encoded data with channels A, C, E, and G aligned to the falling edge of the source synchronous transmit clock and channels B, D, F, and H aligned to the rising edge of the transmit clock. The receive path interface is done in the same manner.

The TLK2208A aligns the recovered data clock frequency to the reference clock on each channel by means of a clock tolerance compensation circuit and internal FIFO that inserts or drops 20-bit IDLE codes as needed in the interpacket gap (IPG). In synchronous mode, the received data for all channels is aligned to a single receive data clock that is a buffered version of the reference clock.

The TLK2208A supports a selectable IEEE 802.3z compliant 8b/10b encoder/decoder in all its modes of operation.

The TLK2208A automatically locks onto incoming data without the need to pre-lock.

The TLK2208A provides a comprehensive series of built-in tests for self-test purposes including loopback and PRBS generation and verification. An IEEE 1149.1 JTAG port is also supported to aid in board manufacturing testing.

The TLK2208A is housed in a small form-factor 19*19-mm, 289-terminal BGA with 1,0-mm ball pitch. The ball out and footprint are compatible with those of the PMC-Sierra PM8352 8-channel transceiver.

The TLK2208A is characterized to support the commercial temperature range of 0°C to 70°C.

The TLK2208A consumes 1.3 W when operating at nominal conditions.

The TLK2208A is designed to be hot-plug capable. A power-on reset puts the serial side output signal terminals

TX+/TX in the high-impedance state during power up.