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The TLK1201 gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.
The primary application of this device is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 or 75 . The transmission media can be printed-circuit board traces,copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The TLK1201I performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.
The TLK1201I supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data,outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first, (bits 0 − 4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5 − 9 of the 8b/10b encoded data) are clocked on the falling edge of the clock.
The device provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.
The TLK1201I is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device's PowerPAD be soldered to the thermal land on the board.
The TLK1201I is characterized for operation from −0°C to 70°C (TLK1201), or −40°C to 85°C (TLK1201I).
The TLK1201I uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps.
The TLK1201I is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state.
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
TLK1201RCP Features
0.6-Gbps to 1.3-Gbps Serializer/Deserializer Low Power Consumption <200 mW at 1.25 Gbps LVPECL Compatible Differential I/O on High Speed Interface Single Monolithic PLL Design Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking Receiver Differential Input Thresholds 200 mV Minimum IEEE 802.3 Gigabit Ethernet Compliant ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant Advanced 0.25-m CMOS Technology No External Filter Capacitors Required Comprehensive Suite of Built-In Testability IEEE 1149.1 JTAG Support 2.5-V Supply Voltage for Lowest Power Operation 3.3-V Tolerant on LVTTL Inputs Hot Plug Protection 64-Pin VQFP With Thermally Enhanced Package (PowerPAD) CPRI Data Rate Compatible (614 Mbps and 1.22 Gbps) Industrial Temperature Range Supported: −40°C to 85°C
The TLK1211RCP gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.
The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 W. The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.
The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.
In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 04 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 59 of the 8b/10b encoded data) are clocked on the falling edge of the clock.
The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.
The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board. The transceiver is characterized for operation from 40°C to 85°C.
The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 250 mW typical power when operating at 1.25 Gbps.
The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state.
TLK1211RCP Maximum Ratings
TLK1211RCP
Supply voltage, VDD (see (2) )
0.3 V to 3 V
Input voltage range at TTL terminals, VI
0.5 V to 4 V
Input voltage range at any other terminal
0.3 V to VDD +0.3 V
Storage temperature, Tstg
65 to 150
Electrostatic discharge
CDM: 1 kV, HBM:4 kV
Characterized free-air operating temperature range
TLK1211RCP
40 to 85
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
TLK1211RCP Features
` 0.6-Gbps to 1.3-Gbps Serializer/Deserializer ` Advanced 0.25-m CMOS Technology ` Low Power Consumption <250 mW (typ) at 1.25 Gbps ` Comprehensive Suite of Built-In Testability ` Fast Relock Times Less Than 256 ns (Typ) Suitable for PON Applications ` 2.5-V Supply Voltage for Lowest Power Operation ` LVPECL Compatible Differential I/O on High Speed Interface ` 3.3-V Tolerant on LVTTL Inputs ` Single Monolithic PLL Design ` Hot Plug Protection ` Support For 10-Bit Interface or Reduced Interface 5-Bit DDR (Double Data Rate) Clocking ` CPRI Data Rate Compatible (614 Mbps,1.22 Gbps) ` Receiver Differential Input Thresholds 200 mV Minimum ` Industrial Temperature Range Supported:40°C to 85°C ` IEEE 802.3 Gigabit Ethernet Compliant ` ANSI X3.230-1994 (FC-PH) Fibre Channel Compliant ` 64-Pin VQFP With Thermally Enhanced Package (PowerPAD™) ` IEEE 1149.1 JTAG Support ` No External Filter Capacitors Required
