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TQ8218, TQ8223, TQ8888

TQ8218, TQ8223, TQ8888 Selling Leads, Datasheet

MFG:N/A  Package Cooled:01+  D/C:TSSOP28

TQ8218, TQ8223, TQ8888 Picture

TQ8218, TQ8223, TQ8888 Datasheet download

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Part Number: TQ8218

 

MFG: N/A

Package Cooled: 01+

D/C: TSSOP28

 

 

 
 
 
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About TQ8004

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Datasheet: TQ8004

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About TQ8223

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Datasheet: TQ8223

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About TQ8004

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TQ8218 General Description

The TQ8218/TQ8219 is a low jitter, high performance optoelectronic driver intended for interfacing LVPECL or CML outputs from a multiplexer or clock recovery device to various O/E evices, including uncooled DFB lasers, high power VCSEL rrays, EA modulators and Mach-Zender modulators. The devices'  ymmetry and level controls, low additive jitter, and excellent rise/ all times while driving significant loads allow the highest system evel performance at low cost. The small footprint makes the evices particularly suitable for high port count WDM applications.

TQ8218 Maximum Ratings

Parameter Symbol Min Maxi Unit
Supply voltage VDD 0 3.5 V
Output stage supply voltage VDRIVE VEE 4.0 V
Output stage supply return VEE -5.5 0 V
PECL inputs   GND-0.5 VDD+0.5 V
Control signals   VEE-0.5 GND+0.5 V
Tstg, Storage Temperature   -55 150 °C
Tj, Maximum junction temperature     150 °C
Electrostatic Discharge (Human Body Model)     1000 V

TQ8218 Features

• High performance fully backterminated
  80mA/4V output
  driver(TQ8218)
• Also available without backterminations for 25
   applications (TQ8219)
• Output can drive 50 external
   optical modulator, 50
   transmission line, or directly
   modulated laser from LVPECL input
• NRZ data rates to 3.125Gbs
• Output symmetry adjust
• LVPECL input
• 65-130pS rise/fall time
• 28 pin TSSOP small outline package
• +3.3, -5V power supply
• 40 to +100°C case operating temperature range

TQ8218 Typical Application

• VCSEL driver
• Driving uncooled DFB lasers
• Single-ended 50 4.0V
  ectro-absorptive modulator river
• 8V differential 50 Mach-Zender river

TQ8218 Connection Diagram

TQ8223 General Description

The TQ8223 is a multi-configuration SONET/SDH OC48/STM16 CDR/ DEMUX that regenerates and re-times serial 2.48832 Gb/s data. It recovers the 2.48832 GHz clock from the data stream and frequency divides it to generate control signals and clocks used to perform the demultiplexing function.

The TQ8223 is extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream is demultiplexed into a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also available. The device generates byte-wise parity check bits for the demultiplexed data and provides associated clock outputs for the different modes. Parity checking is not required for normal device operation. The TQ8223 provides added flexibility through a selectable internal/external Voltage Controlled Oscillator(VCO) as well as a selectable internal Phase Locked Loop (PLL). If an external high frequency clock is utilized a singleended or differential AC coupled clock may be used.

The internal PLL contains a NRZ phase detector which enables it to adjust the phase of the internal clock such that sampling of the incoming data stream occurs in the middle of the the data eye. An offset control allows adjustment ±125 pS around this nominal position. Operating from a single +5V supply, the TQ8223 provides fully compliant functionality and performance.

The TQ8223 is fully compliant with SONET/SDH jitter tolerance and transfer specifications. A TTL level LOCK signal is supplied to indicate when the frequency difference between the internal 38.88 MHz clock and the external 38.88 MHz clock is less than 488 ppm.

TQ8223 Maximum Ratings

Parameter Symbol Min Max Unit
Supply voltage VDD-VEE GND 7.0 V
Internal VCO Supply voltage VOSC VEE-0.5 VDD+0.5 V
DIN,NDIN termination voltage VTD VEE-0.5 VDD+0.5 V
Inputs/Outputs   VEE-0.5 VDD+0.5 V
Storage Temperature Tstg -55 150
Maximum Case Operating Temperature, Tc   125
Maximum junction temperature Tj   120
Electrostatic Discharge (100 pF, 1.5 kW)     1000 V

TQ8223 Features

• Single-chip 1:32 Demultiplexer
  with integrated clock and data recovery
• Differential Analog Data Input
• SONET/SDH compliant for
  2.48832 Gb/s jitter tolerance & transfer
• Internal PLL with NRZ phase
  detector ensures sampling of
  incoming data stream occurs in
  center of data eye
• Static phase adjustment on
  recovered clock position
• High speed input data bit slipper
  for use in framing
• External RC-based loop filter
• Four output clock rates at
  311.04, 155.52, 77.76, and 38.88 MHz.
• Internal byte-wise even/odd
  parity bit generator (mode programable)
• Direct-coupled TTL low-speed outputs
• 23mm 208-pin BGA package
• 5V single supply
• 40 to +125°C case operating temperature.

TQ8223 Connection Diagram

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