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TSB43DA42GHC, TSB43DA42GHCR, TSB43DB42

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Info of TSB43DA42GHC
Info of TSB43DA42GHCR
Info of TSB43DB42

TSB43DA42GHC, TSB43DA42GHCR, TSB43DB42 Selling Leads, Datasheet

MFG:Texas Instruments Category:Integrated Circuits (ICs) Package Cooled:n/a D/C:09+

TSB43DA42GHC, TSB43DA42GHCR, TSB43DB42 Picture

TSB43DA42GHC, TSB43DA42GHCR, TSB43DB42 Datasheet download

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Part Number: TSB43DA42GHC

Category: Integrated Circuits (ICs)

MFG: Texas Instruments

Package Cooled: n/a

D/C: 09+

Description: TSB43DA42GHCR

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TSB43DA42GHC Parameters

Technical/Catalog Information	TSB43DA42GHC
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Controller Type	Link Layer Controller
Interface	IEEE 1394
Voltage - Supply	1.5 V, 3.3 V
Current - Supply	-
Package / Case	196-BGA
Packaging	Tray
Operating Temperature	-20°C ~ 85°C
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	TSB43DA42GHC TSB43DA42GHC

TSB43DA42GHCR Parameters

Technical/Catalog Information	TSB43DA42GHCR
Vendor	Texas Instruments
Category	Integrated Circuits (ICs)
Controller Type	Link Layer Controller
Interface	IEEE 1394
Voltage - Supply	1.5 V, 3.3 V
Current - Supply	-
Package / Case	196-BGA
Packaging	Tape & Reel (TR)
Operating Temperature	-20°C ~ 85°C
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	TSB43DA42GHCR TSB43DA42GHCR

TSB43DB42 General Description

The TSB43DA42/TSB43DB42 are high-performance consumer electronics 1394 link layer and integrated physical layer devices designed for digitally interfacing advanced audio/video consumer electronics applications. SB43DA42/DB42 support formatting and transmission of IEC61883 data; including IEC61883-1 (general), IEC61883-2 (SD-DVCR), IEC61883-4 (MPEG2-TS), IEC61883-5 (SDL-DVCR), IEC61883-6 (audio and music), and IEC61883-7 (ITU-R BO.1294 SystemB-DSS). TSB43DA42/DB42 also supports standard 1394 data types, such as asynchronous, asynchronous streams, and PHY packets.

The TSB43DA42 version incorporates M6 baseline per the 5C specification to support transmit and receive of up to three MPEG2 or audio formatted transport streams with encryption and decryption. The TSB43DA42 version also includes hardware acceleration for content key generation.

The TSB43DB42 version is identical to the TSB43DA42 without implementation of the encryption/decryption features. The TSB43DB42 device allows customers that do not require the encryption/decryption features to incorporate the TSB43DA42 function without becoming DTLA licensees.

The TSB43DA42/TSB43DB42 feature an integrated two-port PHY. The PHY operates at 100 Mbps, 200 Mbps, or 400 Mbps. They follow all requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards.

TSB43DB42 Features

` 1394 Features
   Integrated 400/200/100 Mbps 2-Port PHY
   Compliant to IEEE 1394-1995 and IEEE 1394a-2000 Standards
   Supports Bus Manager Functions and Automatic 1394 Self-ID Verification
   Separate Asyncchronous Ack FIFOs Decrease the Ack-Tracking Burden on External CPU
` DTLA Encryption Support for MPEG2-DVB, DSS, and Audio Data (TSB43DA42 Only)
   Support for up to Three Encrypted/Decrypted Streams at One Time
   Full Ake Performed With Hardware Assist
   Secure Method for Loading DTLA Information Using Ex-CPU Interface
` Audio and Video Interfaces
   Three Configurable High-Speed Data Ports for Video Data
   Two Ports Configurable as Parallel or Serial
   One Port Serial Only
   Two Interfaces for Audio Data (Only One Audio Stream Supported at a Time)
   60958 Port
   I2S-Style DAC Interface for PCM Data (Two Channel)
   Pass-Through Modes for HSDI0 and HSDI1
   Packet Insertion Two Insertion Buffers per HSDI
   PID Filtering (32 PID Filters per HSDI Port)
` External CPU Interfaces
   Motorola 68K-Style 16-Bit Asynchronous Interface (Supports External DMA Only)
   SRAM-Like 16-Bit Asynchronous Interface (Supports External DMA Only)
   PCI Interface (33 MHz) Compliant to PCI Specification Version 2.2 (Supports PCI Slave and Master Function)
` Data Buffers
   3x 4K Byte Isochronous Buffers for Audio and Video Data
   2x 2K Byte Asynchronous/Asynchronous Stream Transmit Buffers
   2x 2K Byte Asynchronous/Asynchronous Stream Receive Buffers
   1x 1K Byte Self-ID Buffer
   Insertion Buffers for MPEG2 PacketInsertion (DAT, PMT, SIT, and DIT)
   Programmable Data/Space AvailableIndicators for Buffer Flow Control
` Hardware Packet Formatting for the Following Standards
   IEC61883-1 (General)
   IEC61883-2 (SD-DVCR)
   IEC61883-4 (MPEG2-TS)
   IEC61883-6 (Audio and Music)
   IEC61883-7 (ITU-R BO.1294 System B)DSS
   Asynchronous Packets
   Asynchronous Streams
   PHY Packets (Including Self-IDs)
` Additional Features
   JTAG Interface to Support Post-Assembly Scan of Device I/O Boundary Scan
   Unique Binding Method for Protecting Sensitive Off-Chip Data From Ex-CPU Interface

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