UJA1061, UJA1065, UJA1065/5V0 Selling Leads, Datasheet
MFG:PHILIPS Package Cooled:7500 D/C:PHI/NXP
UJA1061, UJA1065, UJA1065/5V0 Datasheet download
Part Number: UJA1061
MFG: PHILIPS
Package Cooled: 7500
D/C: PHI/NXP
UJA1061, UJA1065, UJA1065/5V0
- Table of contents:
Info of UJA1061
Info of UJA1065
Info of UJA1065/5V0
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About UJA1061
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Datasheet: UJA1061
File Size: 331622 KB
Manufacturer: PHILIPS [Philips Semiconductors]
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About UJA1065
PDF/DataSheet Download
Datasheet: UJA1065
File Size: 292021 KB
Manufacturer: PHILIPS [Philips Semiconductors]
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About UJA1061
PDF/DataSheet Download
Datasheet: UJA1061
File Size: 331622 KB
Manufacturer: PHILIPS [Philips Semiconductors]
Download : Click here to Download
UJA1061 General Description
The UJA1061 is a System Basis Chip (SBC), replacing basic discrete components that are commonly used in Electronic Control Units (ECUs) for automotive body multiplexing. The UJA1061 supports any body application which controls various power peripherals by using the fault-tolerant CAN as the main physical layer and the LIN physical layer as local sub-bus. The UJA1061 contains the following integrated devices:
The UJA1061 is intended to be used in combination with a microcontroller and a CAN controller. The microcontroller
is the first to come and the last to go in an ECU designed with the UJA1061. In failure situations, the UJA1061 maintains the microcontroller function as long as possible in order to provide full monitoring and software driven fall-back operation.
UJA1061 Features
1.1 General
` Excellent EMC performance
` ± 8 kV ESD protection (human body model) for the outside module pins
` CAN/LIN-bus pins are short-circuit proof to the battery (up to 60 V) and to ground
` Battery and CAN/LIN-bus pins are protected against transients that occur in an automotive environment (ISO7637)
` Software Development mode partly disabling of fail-safe and watchdog functionality to ease software
development
` Unique SPI readable device type identification
` Small footprint HTSSOP32 package (body 6 ´ 11 mm) with low thermal resistance. 1.2 System features
` 12 V, 24 V and 42 V system support with low sleep current (typical 50 mA)
` Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with automatic adaption of interface levels to
microcontrollers
` Flexible, independent external regulator extension via 14 V battery related pin INH (enables fail-safe scalable
supply system)
` Smart operating and power management modes
` In-field Flash Programming mode
` Cyclic wake-up capability in Standby and Sleep mode
` Remote wake-up capability via CAN and LIN buses
` Local WAKE port with cyclic supply feature
` 42 V battery related local wake-up input
` 42 V battery related high-side switch output to drive external loads such as relays and wake-up switches
` Interrupt output with 12 maskable interrupt sources:
Interrupt service monitor
One interrupt per watchdog period to prevent microcontroller overloading; ensures predictable software behaviour
` Extensive set of SPI-readable system diagnostics:
Detection and detailed error reporting on CAN and LIN bus failures (e.g. shorts to GND/BAT, open bus wires, etc.)
TxD dominant and RxD recessive clamping as well as RxD to TxD short detection to prevent bus deadlocks
Local ECU ground-shift detection with two selectable thresholds
Over-temperature warning
Battery monitoring to detect battery interrupt or a chattering battery contact to store data before microcontroller power down (e.g. to store seat position)
Signalling of potential RAM-retention errors due to low microcontroller VCC.
1.3 Fail-safe features
` Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
` Fail-safe coded 16-bit SPI interface to microcontroller, including chip-select pin for multiple SPI devices on the
same bus
` Integrated fail-safe and system features:
Rigorous error handling based on diagnostics
12 dedicated reset sources supporting different, history dependent, software start-up and diagnosis
Global enable pin for control of safety critical hardware
Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. switch on parking lights)
Single SPI message; no assembly of multiple SPI frames
Programmable active-low system reset with detection of both clamped and open reset line to prevent system deadlocks
Fail-safe coded activation of Software Development mode and Flash mode
24-bit access-protected RAM can be used, for instance, for logging of cyclic problems.
1.4 CAN physical layer
` ISO11898-3 compliant fault-tolerant CAN transceiver
` Downwards compatible with TJA1054/TJA1054A
` Enhanced error signalling and reporting
` Separated low-drop-out voltage regulator for CAN bus:
Microcontroller supply independent, autonomous physical layer bus failure management
Significantly improves EMC performance
` Partial networking capability:
Completely passive behaviour to the bus when unpowered
Selective Sleep option with global wake-up allowing selected CAN bus communication without waking-up sleeping nodes.
1.5 LIN physical layer
` LIN2.0 compatible LIN transceiver
` Enhanced error signalling and reporting.
` LIN transceiver compatible with LIN specification, revision 2.0
` Watchdog
` Separate voltage regulators for both host controller and CAN transceiver
` Serial peripheral interface (full duplex)
` Local wake-up input port
` Inhibit output port. In addition to the cost advantages compared with conventional multi-chip solutions, the UJA1061 offers an intelligent combination of system-specific functions such as:
` Advanced low power concept
` Safe and controlled system start-up behaviour
` Advanced fail-safe system behaviour that prevents any deadlock
` Detailed status reporting on system and sub-system (for example, CAN) levels.
` Excellent EMC performance
` ± 8 kV ESD protection (human body model) for the outside module pins
` CAN/LIN-bus pins are short-circuit proof to the battery (up to 60 V) and to ground
` Battery and CAN/LIN-bus pins are protected against transients that occur in an automotive environment (ISO7637)
` Software Development mode partly disabling of fail-safe and watchdog functionality to ease software
development
` Unique SPI readable device type identification
` Small footprint HTSSOP32 package (body 6 ´ 11 mm) with low thermal resistance. 1.2 System features
` 12 V, 24 V and 42 V system support with low sleep current (typical 50 mA)
` Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with automatic adaption of interface levels to
microcontrollers
` Flexible, independent external regulator extension via 14 V battery related pin INH (enables fail-safe scalable
supply system)
` Smart operating and power management modes
` In-field Flash Programming mode
` Cyclic wake-up capability in Standby and Sleep mode
` Remote wake-up capability via CAN and LIN buses
` Local WAKE port with cyclic supply feature
` 42 V battery related local wake-up input
` 42 V battery related high-side switch output to drive external loads such as relays and wake-up switches
` Interrupt output with 12 maskable interrupt sources:
Interrupt service monitor
One interrupt per watchdog period to prevent microcontroller overloading; ensures predictable software behaviour
` Extensive set of SPI-readable system diagnostics:
Detection and detailed error reporting on CAN and LIN bus failures (e.g. shorts to GND/BAT, open bus wires, etc.)
TxD dominant and RxD recessive clamping as well as RxD to TxD short detection to prevent bus deadlocks
Local ECU ground-shift detection with two selectable thresholds
Over-temperature warning
Battery monitoring to detect battery interrupt or a chattering battery contact to store data before microcontroller power down (e.g. to store seat position)
Signalling of potential RAM-retention errors due to low microcontroller VCC.
1.3 Fail-safe features
` Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
` Fail-safe coded 16-bit SPI interface to microcontroller, including chip-select pin for multiple SPI devices on the
same bus
` Integrated fail-safe and system features:
Rigorous error handling based on diagnostics
12 dedicated reset sources supporting different, history dependent, software start-up and diagnosis
Global enable pin for control of safety critical hardware
Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. switch on parking lights)
Single SPI message; no assembly of multiple SPI frames
Programmable active-low system reset with detection of both clamped and open reset line to prevent system deadlocks
Fail-safe coded activation of Software Development mode and Flash mode
24-bit access-protected RAM can be used, for instance, for logging of cyclic problems.
1.4 CAN physical layer
` ISO11898-3 compliant fault-tolerant CAN transceiver
` Downwards compatible with TJA1054/TJA1054A
` Enhanced error signalling and reporting
` Separated low-drop-out voltage regulator for CAN bus:
Microcontroller supply independent, autonomous physical layer bus failure management
Significantly improves EMC performance
` Partial networking capability:
Completely passive behaviour to the bus when unpowered
Selective Sleep option with global wake-up allowing selected CAN bus communication without waking-up sleeping nodes.
1.5 LIN physical layer
` LIN2.0 compatible LIN transceiver
` Enhanced error signalling and reporting.
` LIN transceiver compatible with LIN specification, revision 2.0
` Watchdog
` Separate voltage regulators for both host controller and CAN transceiver
` Serial peripheral interface (full duplex)
` Local wake-up input port
` Inhibit output port. In addition to the cost advantages compared with conventional multi-chip solutions, the UJA1061 offers an intelligent combination of system-specific functions such as:
` Advanced low power concept
` Safe and controlled system start-up behaviour
` Advanced fail-safe system behaviour that prevents any deadlock
` Detailed status reporting on system and sub-system (for example, CAN) levels.
UJA1061 Typical Application
· Low speed, fault-tolerant CAN transceiver, inter-operable and downwards compatible with CAN transceivers TJA1054 and TJA1054A, and compatible with ISO11898-3 standard
· Single 42 V power supply architecture when combined with an external step-down converter
· Single 14 V power supply architecture
· Dual 14 V and 42 V power supply architecture.
· Single 42 V power supply architecture when combined with an external step-down converter
· Single 14 V power supply architecture
· Dual 14 V and 42 V power supply architecture.
UJA1061 Connection Diagram
UJA1065 General Description
The UJA1065 System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The SBC supports all networking applications which control various power and sensor peripherals by using high-speed CAN as the main network interface and LIN as a local sub-bus. The SBC contains the following integrated devices:
• High-speed CAN transceiver, inter-operable and downwards compatible with CAN transceiver TJA1041 and TJA1041A, and compatible with the ISO11898-2 standard and the ISO11898-5 standard (in preparation)
• LIN transceiver compliant with LIN 2.0 and SAE J2602, and compatible with LIN 1.3
• Advanced independant watchdog
• Dedicated voltage regulators for microcontroller and CAN transceiver
• Serial peripheral interface (full duplex)
• Local wake-up input port
• Inhibit / limp home output port
In addition to the advantages of integrating these common ECU functions in a single package, the SBC offers an intelligent combination of system-specific functions such as:
• Advanced low power concept
• Safe and controlled system start-up behavior
• Advanced fail-safe system behavior that prevents any conceivable deadlock
• Detailed status reporting on system and sub-system levels
The UJA1065 is designed to be used in combination with a microcontroller with a CAN controller. The SBC ensures that the microcontroller is always started up in a defined manner. In failure situations the SBC will maintain the microcontroller function for as long as possible, to provide full monitoring and software driven fall-back operation.
The UJA1065 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures.
UJA1065 Features
1 General
Contains a full set of CAN and LIN ECU functions:
·CAN transceiver and LIN transceiver
·Voltage regulator for the microcontroller (3.0 V, 3.3 V or 5.0 V)
·Separate voltage regulator for the CAN transceiver (5 V)
·Enhanced window watchdog with on-chip oscillator
·Serial Peripheral Interface (SPI) for the microcontroller
· ECU power management system
·Fully integrated autonomous fail-safe system
Designed for automotive applications:
· Supports 14 V, 24 V and 42 V architectures
·Excellent ElectroMagnetic Compatibility (EMC) performance
· ± 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off board pins
·± 60 V short-circuit proof CAN / LIN-bus pins
·Battery and CAN / LIN-bus pins are protected against transients in accordance with ISO 7637
·Very low Sleep current
Supports remote flash programming via the CAN-bus
Small 8 mm ´ 11 mm HTSSOP32 package with low thermal resistance
2 CAN transceiver
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Enhanced error signalling and reporting
Dedicated low dropout voltage regulator for the CAN-bus:
·Independent from microcontroller supply
·Guarded by CAN-bus failure management
·Significantly improves EMC performance
Partial networking option with global wake-up feature, allows selective CAN-bus communication without waking up sleeping nodes
Bus connections are truly floating when power is off
SPLIT output pin for stabilizing the recessive bus level
3 LIN transceiver
LIN 2.0 compliant LIN transceiver
Enhanced error signalling and reporting
Downward compatible with LIN 1.3 and the TJA1020
4 Power management
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus and LIN-bus
External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe)
42 V battery related high-side switch for driving external loads such as relays and wake-up switches
Intelligent maskable interrupt output
5 Fail-safe features
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety critical hardware
Detection and detailed reporting of failures:
·On-chip oscillator failure and watchdog alerts
·Battery and voltage regulator undervoltages
·CAN and LIN-bus failures (short-circuits and open-circuit bus wires)
·TXD and RXD clamping situations and short-circuits
·Clamped or open reset line
·SPI message errors
·Overtemperature warning
·ECU ground shift (two selectable thresholds)
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software initiated system reset
Contains a full set of CAN and LIN ECU functions:
·CAN transceiver and LIN transceiver
·Voltage regulator for the microcontroller (3.0 V, 3.3 V or 5.0 V)
·Separate voltage regulator for the CAN transceiver (5 V)
·Enhanced window watchdog with on-chip oscillator
·Serial Peripheral Interface (SPI) for the microcontroller
· ECU power management system
·Fully integrated autonomous fail-safe system
Designed for automotive applications:
· Supports 14 V, 24 V and 42 V architectures
·Excellent ElectroMagnetic Compatibility (EMC) performance
· ± 8 kV ElectroStatic Discharge (ESD) protection Human Body Model (HBM) for off board pins
·± 60 V short-circuit proof CAN / LIN-bus pins
·Battery and CAN / LIN-bus pins are protected against transients in accordance with ISO 7637
·Very low Sleep current
Supports remote flash programming via the CAN-bus
Small 8 mm ´ 11 mm HTSSOP32 package with low thermal resistance
2 CAN transceiver
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Enhanced error signalling and reporting
Dedicated low dropout voltage regulator for the CAN-bus:
·Independent from microcontroller supply
·Guarded by CAN-bus failure management
·Significantly improves EMC performance
Partial networking option with global wake-up feature, allows selective CAN-bus communication without waking up sleeping nodes
Bus connections are truly floating when power is off
SPLIT output pin for stabilizing the recessive bus level
3 LIN transceiver
LIN 2.0 compliant LIN transceiver
Enhanced error signalling and reporting
Downward compatible with LIN 1.3 and the TJA1020
4 Power management
Smart operating modes and power management modes
Cyclic wake-up capability in Standby and Sleep mode
Local wake-up input with cyclic supply feature
Remote wake-up capability via the CAN-bus and LIN-bus
External voltage regulators can easily be incorporated in the power supply system (flexible and fail-safe)
42 V battery related high-side switch for driving external loads such as relays and wake-up switches
Intelligent maskable interrupt output
5 Fail-safe features
Safe and predictable behavior under all conditions
Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
Fail-safe coded 16-bit SPI interface for the microcontroller
Global enable pin for the control of safety critical hardware
Detection and detailed reporting of failures:
·On-chip oscillator failure and watchdog alerts
·Battery and voltage regulator undervoltages
·CAN and LIN-bus failures (short-circuits and open-circuit bus wires)
·TXD and RXD clamping situations and short-circuits
·Clamped or open reset line
·SPI message errors
·Overtemperature warning
·ECU ground shift (two selectable thresholds)
Rigorous error handling based on diagnostics
Supply failure early warning allows critical data to be stored
23 bits of access-protected RAM is available e.g. for logging of cyclic problems
Reporting in a single SPI message; no assembly of multiple SPI frames needed
Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. for switching on warning lights)
Fail-safe coded activation of Software development mode and Flash mode
Unique SPI readable device type identification
Software initiated system reset
UJA1065 Connection Diagram
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