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UJA1061

Features: 1.1 General` Excellent EMC performance` ± 8 kV ESD protection (human body model) for the outside module pins` CAN/LIN-bus pins are short-circuit proof to the battery (up to 60 V) and to ground` Battery and CAN/LIN-bus pins are protected against transients that occur in an automotive envi...

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SeekIC No. : 004536977 Detail

UJA1061: Features: 1.1 General` Excellent EMC performance` ± 8 kV ESD protection (human body model) for the outside module pins` CAN/LIN-bus pins are short-circuit proof to the battery (up to 60 V) and to gr...

UJA1061 Data Sheet

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Part Number:
UJA1061
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

1.1 General
` Excellent EMC performance
` ± 8 kV ESD protection (human body model) for the outside module pins
` CAN/LIN-bus pins are short-circuit proof to the battery (up to 60 V) and to ground
` Battery and CAN/LIN-bus pins are protected against transients that occur in an automotive environment   (ISO7637)
` Software Development mode partly disabling of fail-safe and watchdog functionality to ease software
development
` Unique SPI readable device type identification
` Small footprint HTSSOP32 package (body 6 ´ 11 mm) with low thermal resistance. 1.2 System features
` 12 V, 24 V and 42 V system support with low sleep current (typical 50 mA)
` Support of 2.5, 3.0, 3.3 and 5.0 V microcontrollers with automatic adaption of interface levels to
microcontrollers
` Flexible, independent external regulator extension via 14 V battery related pin INH (enables fail-safe scalable
supply system)
` Smart operating and power management modes
` In-field Flash Programming mode
` Cyclic wake-up capability in Standby and Sleep mode
` Remote wake-up capability via CAN and LIN buses
` Local WAKE port with cyclic supply feature
` 42 V battery related local wake-up input
` 42 V battery related high-side switch output to drive external loads such as relays and wake-up switches
` Interrupt output with 12 maskable interrupt sources:
Interrupt service monitor
One interrupt per watchdog period to prevent microcontroller overloading; ensures predictable software behaviour
` Extensive set of SPI-readable system diagnostics:
Detection and detailed error reporting on CAN and LIN bus failures (e.g. shorts to GND/BAT, open bus wires, etc.)
TxD dominant and RxD recessive clamping as well as RxD to TxD short detection to prevent bus deadlocks
Local ECU ground-shift detection with two selectable thresholds
Over-temperature warning
Battery monitoring to detect battery interrupt or a chattering battery contact to store data before microcontroller power down (e.g. to store seat position)
Signalling of potential RAM-retention errors due to low microcontroller VCC.
1.3 Fail-safe features
` Programmable fail-safe coded window and time-out watchdog with on-chip oscillator, guaranteeing autonomous fail-safe system supervision
` Fail-safe coded 16-bit SPI interface to microcontroller, including chip-select pin for multiple SPI devices on the
same bus
` Integrated fail-safe and system features:
Rigorous error handling based on diagnostics
12 dedicated reset sources supporting different, history dependent, software start-up and diagnosis
Global enable pin for control of safety critical hardware
Limp home output signal for activating application hardware in case system enters Fail-safe mode (e.g. switch on parking lights)
Single SPI message; no assembly of multiple SPI frames
Programmable active-low system reset with detection of both clamped and open reset line to prevent system deadlocks
Fail-safe coded activation of Software Development mode and Flash mode
24-bit access-protected RAM can be used, for instance, for logging of cyclic problems.
1.4 CAN physical layer
` ISO11898-3 compliant fault-tolerant CAN transceiver
` Downwards compatible with TJA1054/TJA1054A
` Enhanced error signalling and reporting
` Separated low-drop-out voltage regulator for CAN bus:
Microcontroller supply independent, autonomous physical layer bus failure management
Significantly improves EMC performance
` Partial networking capability:
Completely passive behaviour to the bus when unpowered
Selective Sleep option with global wake-up allowing selected CAN bus communication without waking-up sleeping nodes.
1.5 LIN physical layer
` LIN2.0 compatible LIN transceiver
` Enhanced error signalling and reporting.
` LIN transceiver compatible with LIN specification, revision 2.0
` Watchdog
` Separate voltage regulators for both host controller and CAN transceiver
` Serial peripheral interface (full duplex)
` Local wake-up input port
` Inhibit output port. In addition to the cost advantages compared with conventional multi-chip solutions, the UJA1061 offers an intelligent combination of system-specific functions such as:
` Advanced low power concept
` Safe and controlled system start-up behaviour
` Advanced fail-safe system behaviour that prevents any deadlock
` Detailed status reporting on system and sub-system (for example, CAN) levels.


Application

· Low speed, fault-tolerant CAN transceiver, inter-operable and downwards compatible with CAN transceivers TJA1054 and TJA1054A, and compatible with ISO11898-3 standard
· Single 42 V power supply architecture when combined with an external step-down converter
· Single 14 V power supply architecture
· Dual 14 V and 42 V power supply architecture.


Pinout

Connection Diagram


Description

The UJA1061 is a System Basis Chip (SBC), replacing basic discrete components that are commonly used in Electronic Control Units (ECUs) for automotive body multiplexing. The UJA1061 supports any body application which controls various power peripherals by using the fault-tolerant CAN as the main physical layer and the LIN physical layer as local sub-bus. The UJA1061 contains the following integrated devices:

The UJA1061 is intended to be used in combination with a microcontroller and a CAN controller. The microcontroller
is the first to come and the last to go in an ECU designed with the UJA1061. In failure situations, the UJA1061 maintains the microcontroller function as long as possible in order to provide full monitoring and software driven fall-back operation.




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