ZL30113LDF1, ZL30116, ZL30116GGG Selling Leads, Datasheet
MFG:ZARLINK Package Cooled:QFN D/C:2008
ZL30113LDF1, ZL30116, ZL30116GGG Datasheet download
Part Number: ZL30113LDF1
MFG: ZARLINK
Package Cooled: QFN
D/C: 2008
ZL30113LDF1, ZL30116, ZL30116GGG
- Table of contents:
Info of ZL30113LDF1
Info of ZL30116
Info of ZL30116GGG
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About ZL30100
PDF/DataSheet Download
Datasheet: ZL30100
File Size: 574385 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
About ZL30100
PDF/DataSheet Download
Datasheet: ZL30100
File Size: 574385 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
About ZL30100
PDF/DataSheet Download
Datasheet: ZL30100
File Size: 574385 KB
Manufacturer: ZARLINK [Zarlink Semiconductor Inc]
Download : Click here to Download
ZL30116 General Description
The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
ZL30116 Features
• Supports the requirements of Telcordia GR-253 and
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and
the requirements of ITU-T G.781 SETS, G.813
SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz that meet jitter
requirements for interfaces up to OC-192/STM-64
• Programmable output synthesizers generate clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently
configurable through a serial software interface
• DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover),
selectable loop bandwidth and pull-in range
• DPLL2 provides a comprehensive set of features
necessary for generating derived output clocks and
other general purpose clocks
• Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Supports master/slave configuration for AdvancedTCATM
• Configurable input to output delay and output to output phase alignment
• Optional external feedback path provides dynamic input to output delay compensation
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity and frequency
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and
the requirements of ITU-T G.781 SETS, G.813
SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz that meet jitter
requirements for interfaces up to OC-192/STM-64
• Programmable output synthesizers generate clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently
configurable through a serial software interface
• DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover),
selectable loop bandwidth and pull-in range
• DPLL2 provides a comprehensive set of features
necessary for generating derived output clocks and
other general purpose clocks
• Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Supports master/slave configuration for AdvancedTCATM
• Configurable input to output delay and output to output phase alignment
• Optional external feedback path provides dynamic input to output delay compensation
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity and frequency
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
ZL30116 Typical Application
• AdvancedTCATM Systems
• Multi-Service Edge Switches or Routers
• Multi-Service Provisioning Platforms (MSPPs)
• Add-Drop Multiplexers (ADMs)
• Wireless/Wireline Gateways
• Wireless Base Stations
• DSLAM / Next Gen DLC
• Core Routers
• Multi-Service Edge Switches or Routers
• Multi-Service Provisioning Platforms (MSPPs)
• Add-Drop Multiplexers (ADMs)
• Wireless/Wireline Gateways
• Wireless Base Stations
• DSLAM / Next Gen DLC
• Core Routers
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