ZL30102

Features: • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock• Supports Telcordia GR-1244-CORE Stratum 4 and 4E• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces• Su...

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SeekIC No. : 004550941 Detail

ZL30102: Features: • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock• Supports Telcordia GR-1244-CORE Stratum...

floor Price/Ceiling Price

Part Number:
ZL30102
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock
• Supports Telcordia GR-1244-CORE Stratum 4 and 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Simple hardware control interface
• Manual and Automatic hitless reference switching
• Accepts three input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 3.088 MHz, 6.312 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1x10-7
• Provides Lock, Holdover and selectable Out of Range indication
• Attenuates wander from 1.8 Hz
• Less than 0.6 nspp intrinsic jitter on all output clocks
• External master clock source: Clock Oscillator or Crystal




Application

• Synchronization and timing control for multi-trunk DS1/ E1 terminal systems such as DSLAMs, Gateways and PBXs
• Clock and frame pulse source for H.110 CT Bus, ST-BUS, GCI and other time division multiplex (TDM) buses



Pinout

  Connection Diagram


Specifications

  Parameter Symbol Min. Max. UNIT
1 Supply voltage V DD_R -0.5 4.6 V
2 Core supply voltage V CORE_R -0.5 2.5 V
3 Voltage on any digital pin VPIN -0.5 6 V
4 Voltage on OSCi and OSCo pin VOSC -0.3 VDD + 0.3 V
5 Current on any pin IPIN   30 mA
6 Storage temperature TST -55 125
7 TQFP 64 pin package power dissipation PPD   500 mW
8 ESD rating VESD   2 kV

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
* Voltages are with respect to ground (GND) unless otherwise stated.



Description

The ZL30102 DS1/E1 Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for DS1/E1 transmission equipment deploying redundant network clocks.

The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references or to another system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between the primary aster-clock and secondary master clock outputs even in the presence of high network jitter.

The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.




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