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ZL50073GAC, ZL50074GA, ZL50075

Table of contents:
Info of ZL50073GAC
Info of ZL50074GA
Info of ZL50075

ZL50073GAC, ZL50074GA, ZL50075 Selling Leads, Datasheet

MFG:ZAR Package Cooled:32 D/C:906

ZL50073GAC, ZL50074GA, ZL50075 Datasheet download

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Part Number: ZL50073GAC

MFG: ZAR

Package Cooled: 32

D/C: 906

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ZL50075 General Description

The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion from input data channel to output data channel.

The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to the input clock or to the internal system clock.

The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are connected to multiple TDM components or circuits. These include:
• Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams connected through different data paths
• Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of clock and frame pulse options
• Support of both ST-BUS and GCI-Bus formats

The ZL50075 also has a number of value added features for voice and data applications:
• Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity applications
• Per-channel A-Law/-Law Conversions for both voice and data
• 64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated Bit Error Rate (BER) test capability to facilitate data path integrity checking

The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.

A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola or Intel-type microprocessors.

The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

ZL50075 Maximum Ratings

Characteristics	Sym.	Min.	Max.	Unit
Chip I/O Supply Voltage Chip Core Supply Voltage Input Voltage (non-5 V tolerant inputs)	V_{DD_IO} V_{DD_CORE} V_{I_3V}	-0.5 -0.5 -0.5	5.0 5.0 V_{DD_IO} + 0.5	V V V
Input Voltage (5 V tolerant inputs)	V_{I_5V}	-0.5	7.0	V
Continuous Current at digital outputs Package power dissipation	I_o P_D		15 2.1	mA W
Storage temperature	T_S	- 55	+125

Note 1: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Note 2: Typical figures are at 25, V_{DD_CORE} at 1.8 V and V_{DD_IO} at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.

ZL50075 Features

• 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at 65.536 Mbps or 32.768 Mbps or using a combination of rates
• 16,384 channel x 16,384 channel non-blocking digital TDM switch at 16.384 Mbps
• 8,192 channel x 8,192 channel non-blocking digital TDM switch at 8.192 Mbps
• High jitter tolerance with multiple input clock sources and frequencies
• Up to 64 serial TDM input streams, divided into 32 groups with 2 input streams per group
• Up to 64 serial TDM output streams, divided into 32 groups with 2 output streams per group
• Per-group input and output data rate conversion selection at 65.536 Mbps, 32.768 Mbps, 16.384 Mbps and 8.192 Mbps. Input and output data group rates can differ
• Per-group input bit delay for flexible sampling point selection
• Per-group output fractional bit advancement
• Two sets of output timing signals for interfacing additional devices
• Per-channel A-Law/-Law Translation
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per-stream Bit Error Rate (BER) test circuits
• Per-channel high impedance output control
• Per-channel force high output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16 bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards forinput and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5V tolerant inputs; 1.8 V core voltage

ZL50075 Typical Application

• Large Switching Platforms
• Central Office Switches
• Wireless Base Stations
• Multi-service Access Platforms
• Media Gateways

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