ZL50015

• 1024 channel x 1024 channel non-blocking dig ital Time Division Multiplex (TDM) switch at 4.096, 8.192 and 16.384 Mbps or using a combination of ports running at 2.048, 4.096, 8.192 and 16.384 Mbps
• 16 serial TDM input, 16 serial TDM output streams
• Integrated Digital Phase-Locked Loop (DPLL) exceeds Telcordia GR-1244-CORE Stratum 4E specifications
• Output clocks have less than 1 ns of jitter (except for the 1.544 MHz output)
• DPLL provides holdover, freerun and jitter attenuation features with four independent reference source inputs
• Exceptional input clock cycle to cycle variation tolerance (20 ns for all rates)
• Output streams can be configured as bidirectional for connection to backplanes
• Per-stream input and output data rate conversion selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Input and output data rates can differ
• Per-stream high impedance control outputs (STOHZ) for 8 output streams
• Per-stream input bit delay with flexible sampling point selection
• Per-stream output bit and fractional bit advancement
• Per-channel ITU-T G.711 PCM A-Law/-Law Translation
• Four frame pulse and six reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per Stream (16) Bit Error Rate Test circuits complying to ITU-O.151
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage