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ZL50114, ZL50114GA, ZL50114-GAG

Table of contents:
Info of ZL50114
Info of ZL50114GA
Info of ZL50114-GAG

ZL50114, ZL50114GA, ZL50114-GAG Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:QFP D/C:09+

ZL50114, ZL50114GA, ZL50114-GAG Datasheet download

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Part Number: ZL50114

MFG: ZARLINK

Package Cooled: QFP

D/C: 09+

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ZL50114 Parameters

ZL50114 Features

128 bi-directional 64 kbps channels in structured, synchronous CES
4 T1/E1 unstructured, asynchronous CES, with integral per stream clock recovery
Interface either directly to LIU, via a framer, or via a TDM backplane
Dual reference Stratum 3, 4 and 4E PLL for synchronous operation
3 x 100 Mbps MII or Dual Redundant 1000 Mbps GMII/PCS(TBI) Ethernet Interfaces
Flexible 32 bit host CPU interface (Motorola PowerQUICC™ II compatible)
On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
Flexible, multi-protocol packet encapsulation
Packet sequencing to allow lost packet detection
Four classes of service with programmable priority mechanisms (WFQ and SP)
Classification of incoming packets at layers 2, 3, 4, and 5

ZL50114 General Description

128 Channel (4 T1/E1) Circuit Emulation Services over Packet CESoP Processor

ZL50114 Maximum Ratings

Parameter	Symbol	Min.	Max.	Units
I/O Supply Voltage	V _{DD_IO}	-0.5	5.0	V
Core Supply Voltage	V _{DD_CORE}	-0.5	2.5	V
PLL Supply Voltage	V _{DD_PLL}	-0.5	2.5	V
Input Voltage	V _I	-0.5	V_DD + 0.5	V
Input Voltage (5 V tolerant inputs)	V _{I_5V}	-0.5	7.0	V
Continuous current at digital inputs	I_IN	-	±10	mA
Continuous current at digital outputs	I_O	-	±15	mA
Package power dissipation	P_D	-	3	W
Storage Temperature	T_S	-55	+125

* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage measurements are with respect to ground (VSS) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.

ZL50114 Features

128 bi-directional 64 kbps channels in structured, synchronous CES
4 T1/E1 unstructured, asynchronous CES, with integral per stream clock recovery
Interface either directly to LIU, via a framer, or via a TDM backplane
Dual reference Stratum 3, 4 and 4E PLL for synchronous operation
3 x 100 Mbps MII or Dual Redundant 1000 Mbps GMII/PCS(TBI) Ethernet Interfaces
Flexible 32 bit host CPU interface (Motorola PowerQUICC™ II compatible)
On-chip packet memory for self-contained operation, with buffer depths of over 16 ms
Flexible, multi-protocol packet encapsulation
Packet sequencing to allow lost packet detection
Four classes of service with programmable priority mechanisms (WFQ and SP)
Classification of incoming packets at layers 2, 3, 4, and 5

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