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ZL50405GD, ZL50409, ZL50409GD

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Info of ZL50405GD
Info of ZL50409
Info of ZL50409GD

ZL50405GD, ZL50409, ZL50409GD Selling Leads, Datasheet

MFG:ZARLINK Package Cooled:0329+ D/C:BGA

ZL50405GD, ZL50409, ZL50409GD Datasheet download

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Part Number: ZL50405GD

MFG: ZARLINK

Package Cooled: 0329+

D/C: BGA

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ZL50409 General Description

The ZL50409 is a low density, low cost, high performance, non-blocking Ethernet switch chip. A single chip provides 8 ports at 10/100 Mbps, 1 uplink port at 10/100 Mbps, and a CPU interface for managed, lightly managed and unmanaged switch applications. The chip supports up to 4 K MAC addresses and up to 4 K tagged-based Virtual LANs (VLANs).

With strict priority and/or WFQ transmission scheduling and WRED dropping schemes, the ZL50409 provides powerful QoS functions for various multimedia and mission-critical applications. The chip provides 2 transmission priorities (4 priorities for uplink port) and 2 levels of dropping precedence. Each packet is assigned a transmission priority and dropping precedence based on the VLAN priority field in a VLAN tagged frame, or the DS/TOS field, or the UDP/TCP logical port fields in IP packets. The ZL50409 recognizes a total of 16 UDP/TCP logical ports, 8 hard-wired and 8 programmable (including one programmable range).

The ZL50409 provides the ability to monitor a link, detect a simple link failure, and provide notification of the failure to the CPU. The CPU can then failover that link to an alternate link.

The ZL50409 supports up to 8 groups of port trunking/load sharing. Each group can contain up to 8 ports. Port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth.

In half-duplex mode, all ports support backpressure flow control, to minimize the risk of losing data during long activity bursts. In full-duplex mode, IEEE 802.3x flow control is provided. The ZL50409 also supports a per-system option to enable flow control for best effort frames, even on QoS-enabled ports.

Statistical information for SNMP and the Remote Monitoring Management Information Base (RMON MIB) are collected independently for all ports. Access to these statistical counters/registers is provided via the CPU interface. NMP Management frames can be received and transmitted via the CPU interface, creating a complete network management solution.

The ZL50409 is fabricated using 0.18 micron technology. The ZL50409 is packaged in a 208-pin Ball Grid Array package.

ZL50409 Maximum Ratings

Storage Temperature	-65 to +150
Operating Temperature	-40 to +85
Maximum Junction Temperature	+125
Supply Voltage V_CC with Respect to V_SS	+2.95 V to +3.65 V
Supply Voltage V_DD with Respect to V_SS	+1.60 V to +2.00 V
Voltage on 5 V Tolerant Input Pins	-0.5 V to (V_CC + 2.5 V)
Voltage on Other Pins	-0.5 V to (V_DD + 0.3 V)

Caution: Stress above those listed may damage the device. Exposure to the Absolute Maximum Ratings for extended periods may affect device reliability. Functionality at or above these limits is not implied.

ZL50409 Features

• Integrated Single-Chip 10/100 Ethernet Switch
• Eight 10/100 Mbps auto-negotiating Fast Ethernet (FE) ports with RMII, MII, GPSI, Reverse MII & Reverse GPSI interface options
• One 10/100 Mbps auto-negotiating port with MII interface option, that can be used as a WAN uplink or as a 9th port
• a 10/100 Mbps Fast Ethernet (FE) CPU port with Reverse MII interface option
• Embedded 2 Mbits (256 KBytes) internal memory
• supports up to 4 K byte frames
• L2 switching
• MAC address self learning, up to 4 K MAC addresses using internal table
• Supports IP Multicast with IGMP snooping, up to 4 K IP Multicast groups
• Supports the following spanning standards
- IEEE 802.1D spanning tree
- IEEE 802.1w rapid spanning tree
• Supports Ethernet multicasting and broadcasting and flooding control
• VLAN Support
• Supports port-based VLAN and tagged-based VLAN (IEEE 802.1Q), up to 4 K VLANs
• Supports both shared VLAN learning (SVL) and independent VLAN learning (IVL)
• CPU access supports the following interface options:
• 8/16-bit parallel and Serial+MII interface in managed mode
• Serial interface in lightly managed mode, or in unmanaged mode with optional I2C EEPROM interface
• Failover Features
• Rapid link failure detection using hardware-generated heartbeat packets
• link failover in less than 50 ms
• Rate Control (both ingress and egress)
• Bandwidth rationing, Bandwidth on demand, SLA (Service Level Agreement)
• Smooth out traffic to uplink port
• Ingress Rate Control
- Back pressure
- Flow Control
- WRED (Weighted Random Early Discard)
• Egress Rate Control
• Down to 16 kbps Rate Control granularity
• Per queue traffic shaper on uplink port
• Packet Filtering and Port Security
• Static address filtering for source and/or destination MAC
• Static MAC address not subject to aging
• Secure mode freezes MAC address learning (each port may independently use this mode)
• Supports port authentication (IEEE 802.1x)
• QoS Support
• Supports IEEE 802.1p/Q Quality of Service with 2 transmission priority queues (4 for uplink port), with strict priority and/or WFQ service disciplines
• Provides 2 levels of dropping precedence with WRED mechanism
• User controls the WRED thresholds.
• Buffer management: per class and per port buffer reservations
• Port-based priority: VLAN priority in a tagged frame can be overwritten by the priority of Port VLAN ID
• Supports per-system option to enable flow control for best effort frames even on QoS enabled ports
• Classification based on:
• Port based priority
• VLAN Priority field in VLAN tagged frame
• DS/TOS field in IP packet
• UDP/TCP logical ports: 8 hard-wired and 8 programmable ports, including one programmable range
• The precedence of the above classifications is programmable
• Supports IEEE 802.3ad link aggregation
• Up to 8 trunk groups, with up to 8 ports per group
• Supports load sharing among trunk ports based on:
- Source port
- Source and/or destination MAC address
• Supports module hot swap on all ports
• MIB Statistics counters for all ports
• Full Duplex Ethernet IEEE 802.3x Flow Control
• Backpressure flow control for Half Duplex ports
• Hardware auto-negotiation through MII management interface (MDIO) for Ethernet ports
• Built-in reset logic triggered by system malfunction
• Built-In Self Test for internal SRAM
• IEEE-1149.1 (JTAG) test port

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