Features: • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC- 2000 PLD Gates- 64 and 32 I/O Pin Versions, Four Dedicated Inputs- 64 Registers- High Speed Global Interconnect- Wide Input Gating for Fast Counters, StateMachines, Address Decoders, etc.- Small Logic Block Size for Random Logic- 100% Fu...
2064VE: Features: • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC- 2000 PLD Gates- 64 and 32 I/O Pin Versions, Four Dedicated Inputs- 64 Registers- High Speed Global Interconnect- Wide Input Gating for Fa...
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The ispLSI 2064VE is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems.
The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1.B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.