2308-2DCGI8 General Description
HI SPD PHASE LOCK LOOP
2308-2DCGI8 Maximum Ratings
| Input Frequency | 10-133 MHz |
| No. of Inputs | 1 |
| Temperature | I |
| Output Frequency | 10-133 MHz |
| No. of Outputs | 2 x 4 |
| Voltage | 3.3 V |
| Package | SOIC 16 |
| Speed | NA |
| Input | 3.3 V LVTTL |
| Output | 3.3 V LVTTL |
| Output Skew | 0.2 ns |
| Max Prop Delay | 0.25 ns |
| Multiply | 2 |
| Divide | |
| Jitter cycle-to-cycle | 0.4 ns |
| Type | Zero Delay Buffer |
Map list: ABCDEFGHIJKLMNOPQRSTUVWXYZ 0123456789All