23892

·  IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test mode.
·  Clock recovery from PLL lock to random data patterns.
·  Guaranteed transition every data transfer cycle
·  Chipset (Tx + Rx) power consumption < 600 mW (typ) @ 80 MHz
·  Single differential pair eliminates multi-channel skew
·  800 Mbps serial Bus LVDS data rate (at 80 MHz clock)
·  10-bit parallel interface for 1 byte data plus 2 control bits
·  Synchronization mode and LOCK indicator
·  Programmable edge trigger on clock
·  High impedance on receiver inputs when power is off
·  Bus LVDS serial output rated for 27W load
·  Small 49-lead BGA package

Supply Voltage (V_CC) ..........................−0.3V to +4V
LVCMOS/LVTTL Input
Voltage ....................................−0.3V to (V_CC +0.3V)
LVCMOS/LVTTL Output
Voltage ....................................−0.3V to (V_CC +0.3V)
Bus LVDS Receiver Input
Voltage .............................................−0.3V to +3.9V
Bus LVDS Driver Output
Voltage .............................................−0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration ................................................10mS
Junction Temperature ....................................+150
Storage Temperature ......................−65 to +150
Lead Temperature
(Soldering, 4 seconds) ...................................+220
Maximum Package Power Dissipation Capacity
@ 25 Package:
49L BGA ..........................................................1.47 W
Package Derating:.........................11.8 mW/ above
49L BGA  ...........................................................+25
_ja ..................................................................85/W
ESD Rating
HBM ....................................................................>2kV
MM ...................................................................> 250V

The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921226 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock.

Both SCAN921025 are compliant with IEEE 1149.1 Standard for Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.

The SCAN921025 transmits data over backplanes or cable.

The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-todata and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921025 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 30 MHz and 80 MHz.