24007

` Best Price/Performance Floating-Point Digital Signal Processor (DSP) TMS320C6712
  10-ns Instruction Cycle Time
  100-MHz Clock Rate
  Eight 32-Bit Instructions/Cycle
  600 MFLOPS
  C6712 and C6211/C6711 are Pin-Compatible
` VelociTI^TM Advanced Very Long Instruction Word (VLIW) C67x^TM DSP Core
  Eight Highly Independent Functional Units:
  Four ALUs (Floating- and Fixed-Point)
  Two ALUs (Fixed-Point)
  Two Multipliers (Floating- and Fixed-Point)
  Load-Store Architecture With 32 32-Bit General-Purpose Registers
  Instruction Packing Reduces Code Size
  All Instructions Conditional
` Instruction Set Features
  Hardware Support for IEEE Single-Precision and Double-Precision Instructions
  Byte-Addressable (8-, 16-, 32-Bit Data)
  8-Bit Overflow Protection
  Saturation
  Bit-Field Extract, Set, Clear
  Bit-Counting
  Normalization
` L1/L2 Memory Architecture
  32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
  32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
  512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  1024M-Byte Addressable External Memory Space
` Device Configuration
  Boot Mode: 8- and 16-Bit ROM Boot
  Endianness: Little Endian, Big Endian
` 16-Bit External Memory Interface (EMIF)
  Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
  Glueless Interface to Asynchronous Memories: SRAM and EPROM
` Enhanced Direct-Memory-Access (EDMA) Controller
` Two Multichannel Buffered Serial Ports (McBSPs)
  Direct Interface to T1/E1, MVIP, SCSA Framers
  ST-Bus-Switching Compatible
  Up to 256 Channels Each
  AC97-Compatible
  Serial-Peripheral-Interface (SPI) Compatible (MotorolaE)
` Two 32-Bit General-Purpose Timers
` Flexible Phase-Locked-Loop (PLL) Clock Generator
` IEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
` 256-Pin Ball Grid Array (BGA) Package (GFN Suffix)
` 0.18-mm/5-Level Metal Process
  CMOS Technology
` 3.3-V I/Os, 1.8-V Internal

absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 2.3 V
Supply voltage range, DV_DD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 4 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to 4 V
Operating case temperature range, T_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 90
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V_SS.

The TMS320C67x^TM DSPs (including the TMS320C6712 device) are the floating-point DSP family in the TMS320C6000^TM DSP platform. The TMS320C6712 (C6712) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 600 million floating-point operations per second (MFLOPS) at a clock rate of 100 MHz, the C6712 device is the lowest-cost DSP in the C6000E DSP platform. The C6712 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. TMS320C67x^TM has 32 general-purpose registers of 32-bit word length and eight highly independent functional units.

The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712 can produce two multiply-accumulates (MACs) per cycle for a total of 200 million MACs per second (MMACS).

The C6712 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The C6712 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows^TM debugger interface for visibility into source code execution.