25C320

Features:

• SPI modes 0,0 and 1,1
• 3.0 MHz Clock Rate
• Single 5V Supply
• Low Power CMOS Technology
   - Max Write Current: 5 mA
   - Read Current: 1.0 mA at 5.5V, 3MHz
   - Standby Current: 1A typical
• 4096 x 8 Organization
• 32 Byte Page
• Sequential Read
• Self-timed ERASE and WRITE Cycles
• Block Write Protection
   - Protect none, 1/4, 1/2, or all of Array
• Built-in Write Protection
   - Power On/Off Data Protection Circuitry
   - Write Enable Latch
   - Write Protect Pin
• High Reliability
   - Endurance: 1M cycles (guaranteed)
   - Data Retention: >200 years
   - ESD protection: >4000V
• 8-pin PDIP/SOIC, 14-pin TSSOP
• Temperature ranges supported
   - Commercial (C):      0 to +70
   - Industrial (I):          -40 to +85
   - Automotive (E):      -40 to +125

Pinout




Specifications

Vcc...................................................................................7.0V
All inputs and outputs w.r.t. Vss..................-0.6V to Vcc+1.0V
Storage temperature.......................................-65 to 150
Ambient temperature under bias.....................-65  to 125
Soldering temperature of leads (10 seconds).............+300
ESD protection on all pins.................................................4kV

Description

The Microchip Technology Inc. 25AA640/25LC640/25C640 (25xx640 ) is a 64K bit serial Electrically  Erasable PROM (EEPROM). The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus.The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS ) input, allowing anynumber of devices to share the same bus.

There are two other inputs that provide the end user with additional flexibility.  Communication to  25AA640/25LC640/25C640 (25xx640 ) can be paused via the hold pin (HOLD ). While the device is paused, transi-tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Also write operations to the Status Register can be disabled via the write protect pin ( WP ).