28C64A

Features:

* Fast Read Access Time-150 ns
* CMOS Technology for Low Power Dissipation
- 30 mA Active
- 100 m A Standby
* Fast Byte Write Time-200 m s or 1 ms
* Data Retention >200 years
 
* High Endurance - Minimum 100,000 Erase/Write
Cycles
* Automatic Write Operation
- Internal Control Timer
- Auto-Clear Before Write Operation
- On-Chip Address and Data Latches
* Data Polling
* Ready/Busy
* Chip Clear Operation
* Enhanced Data Protection
-VCC Detector
- Pulse Filter
- Write Inhibit
* Electronic Signature for Device Identification
* 5-Volt-Only Operation
* Organized 8Kx8 JEDEC Standard Pinout
- 28-pin Dual-In-Line Package
- 32-pin PLCC Package
- 28-pin Thin Small Outline Package (TSOP)
8x20mm
- 28-pin Very Small Outline Package (VSOP)
8x13.4mm
* Available for Extended Temperature Ranges:
- Commercial:  0  to +70


Pinout

Specifications

V_CC and input voltages w.r.t. V_SS.......-0.6V to + 6.25V
Voltage on OE w.r.t. V_SS .....................-0.6V to +13.5V
Voltage on A9 w.r.t. V _SS ......................-0.6V to +13.5V
Output Voltage w.r.t. V _SS................ -0.6V to V_CC+0.6V
Storage temperature..........................-65  to +125

Ambient temp. with power applied.......-50  to +95

*Notice:  Stresses above those listed under "Maximum Ratings"may cause permanent damage to the device.  This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied.  Exposure to maximum rating conditions for extended periods may affect device reliability.

Description

The Microchip Technology Inc. 28C64A is a CMOS 64K nonvolatile electrically Erasable PROM.  The 28C64A  is
accessed like a static RAM for the read or write cycles without the need of external components.  During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations.  Following the initiation of write cycle, 28C64A will go to a busy state and automatically clear and write the latched data using an internal control timer.  To determine when the write cycle is complete, the user has a choice of monitoring the Ready/ Busy output or using Data polling. The Ready/Busy pin is an open drain output, which allows easy configuration in wiredor systems.  Alternatively, Data polling allows the user to read the location last written to when the write operation is complete.  CMOS design and processing enables 28C64A to be used in systems where reduced power consumption and reliability are required.  A complete family of packages is offered
to provide the utmost flexibility in applications