28LV64A

Features:

• 2.7V to 3.6V Supply
• Read Access Time-300 ns
• CMOS Technology for Low Power Dissipation
   - 8 mA Active
   - 50 µA CMOS Standby Current
• Byte Write Time-3 ms
• Data Retention >200 years
• High Endurance - Minimum 100,000  Erase/Write Cycles
• Automatic Write Operation
   - Internal Control Timer
   -  Auto-Clear Before Write Operation
   - On-Chip Address and Data Latches
• DataPolling
• Ready/ Busy
• Chip Clear Operation
• Enhanced Data Protection
   -VCC Detector
   - Pulse Filter
   - Write Inhibit
• Electronic Signature for Device Identification
• Organized 8Kx8 JEDEC Standard Pinout
   - 28-pin Dual-In-Line Package
   - 32-pin Chip Carrier (Leadless or Plastic)
   - 28-pin Thin Small Outline Package (TSOP) 8x20mm
   -  28-pin Very Small Outline Package (VSOP) 8x13.4mm
• Available for Extended Temperature Ranges:
   - Commercial: 0˚C to +70˚C 
   - Industrial: -40˚C to +85˚C


Pinout




Specifications

VCC and input voltages w.r.t. V_SS ...... -0.6V to + 6.25V
Voltage on OE w.r.t. V_SS...................... -0.6V to +13.5V
Voltage on A9 w.r.t. V_SS....................... -0.6V to +13.5V
Output Voltage w.r.t. V_SS............... -0.6V to VCC+0.6V
Storage temperature .......................... -65˚C to +150˚C
Ambient temp. with power applied .....-55°C to +125°C


Description

The Microchip Technology Inc. 28LV64A is a CMOS 64K non-vol-atile electrically Erasable PROM organized as 8K words by 8 bits.The 28LV64A  is accessed like a static RAM for the read or write cycles without the need of external components.  During a "byte write", the address and data are latched internally, freeing the microprocessor address and data bus for other operations.  Fol-lowing the initiation of write cycle, 28LV64A will go to a busy state and automatically clear and write the latched data using an inter-nal control timer.  To determine when the write cycle is complete,the user has a choice of monitoring the Ready/Busy output or using Data polling. The Ready/Busy pin is an open drain output,which allows easy configuration in 'wired-or' systems.  Alterna- tively, Data polling allows the user to read the location last written to when the write operation is complete.  CMOS design and pro-cessing enables this part to be used in systems where reduced power consumption and reliability are required.  A complete family of packages is offered to provide the utmost flexibility in applica-tions.