2SD2611

      The 2SD2611 is a Power Transistor(80V, 7A).The 2SD2611 has 5 features including low saturation,typically VCE(sat)=0.3V at Ic/IB=4/0.4A;excellent DC current gain characterisitics;Pc=30W(TC=25°C);wide SOA(safe operating area);Complements the 2SB1672.
      The absolute maximun ratings of the 2SD2611 are at Ta=25°C, Collector-Base Voltage VCBO is 100V;Collector-Emitter Voltage VCEO is 80V;Emitter-Base Voltage VEBO is 5 V;Collector Current IC(DC) is 7A;collector power dissipation is 30W(Tc=25°C);Junction temperature is 150°C maxnimum;Storage temperature is -55 to +150°C.
      The 2SD2611 Series (Secure FPSLIC family) shown in Table 1 is a combination of the popular Atmel AT40K Series SRAM FPGAs, the AT17 Series Configuration Memories and the high-performance Atmel AVR 8-bit RISC microcontroller with standard peripher- als. Extensive data and instruction SRAM as well as device control and management logic are included in this multi-chip module (MCM). Each DCP can be used as a three-terminal potentio- meter or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, the implementation of ladder networks, and three resistor programmable networks. 
      The device class designator is a single letter identifying the product assurance level as listed below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q designators will not be included in the PIN and will not be marked on the device.Hynix HYMD232G726B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris- ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and burst lengths allow variety of device operation in high performance memory system. 
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