3D7424

monolithic delay line. Delay values, programmed via the serial interface, can be independently varied over 15 equal steps. The step size (in ns) is determined by the device dash number. Each input is reproduced at the corresponding output without inversion, shifted in time as per user selection. For each line, the delay time is given by:  TD_n = T0 + A_n * TI where T0 is the inherent delay, An is the delay address of the n-th line and TI  s the delay increment (dash number). The desired addresses are shifted into the device via the SC and SI  nputs, and the addresses are latched using the AL input. The serial interface can also be used to   able/disable each delay line. The 3D7424 operates at 5 volts and has a typical T0 of 6ns. The 3D7424 is  TL/CMOS-compatible, capable of sourcing or sinking 4mA loads, and features both rising- and falling-edge  ccuracy. The device is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount  4-pin SOIC.