405GPr

      The 405GPr  has the following features including PowerPC 405 32-bit RISC processor core operating up to 400MHz with 16KB I- and D-caches;Synchronous DRAM (SDRAM) interface operating  up to 133MHz;4KB on-chip memory (OCM);External peripheral bus;DMA support for external peripherals, internal  UART and memory;PCI Revision 2.2 compliant interface (32-bit, up to 66MHz).
     Designed specifically to address embedded applications, the PowerPC 405GPr (PPC405GPr)  provides a high-performance, low-power solution that interfaces to a wide range of peripherals by  incorporating on-chip power management features  and lower power dissipation requirements.This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O.The 405GPr incorporates two simple and separate address maps. The first address map defines the possible use of address regions that the processor can access. The second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the 405GPr processor through the use of  mtdcr and mfdcr instructions.
      The 405GPr Memory Controller core provides a low latency access path to SDRAM memory. A variety of  system memory configurations are supported. The memory controller 405GPr supports up to four physical banks. Up to  256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable.The PPC405GPr embedded controller is available as a 456-ball E-PBGA leaded or lead-free package. The 456- ball package is available in two sizes35 millimeters and 27 millimeters. In this section there are two tables that correlate the external signals to the physical package pin (ball) on which they appear.The following table lists all the external signals in alphabetical order and shows the ball number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list"once for each signal name on the ball. The page number listed gives the page in "Signal Functional Description" on page30 where the signalin the indicated interface group begin.