43552

Supply voltage range, VCC . . . . . . . . . . . . . . . . .0.5 V to 7 V 
Input voltage range, VI (see Note 1)  . . . .  . . ... 0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . .0.5 V to 7 V 
Output voltage range applied in the high or low state, 
VO (see Notes 1 and 2)  . . . ......... . ......0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . .. .. . .20 mA
Output clamp current, IOK (VO < 0 or VO >.. VCC) . . . . ±50 mA 
Continuous output current, IO (VO = 0 to VCC)........... ±35 mA . 
Continuous current through VCC or GND . . . . . . . . . . .±70 mA 
Package thermal impedance, JA (see Note 3):
 DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92°C/W
DW package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W 
NS package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60°C/W
PW package  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83°C/W
Storage temperature range, Tstg  . . . . . . . . ..65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

These LV240A octal buffers/drivers are designed for 2-V to 5.5-V VCC operation. The 'LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These LV240A are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.