Features: `ICC reduced by 50%
` Outputs source/sink 24 mA
` 'ACT109 has TTL-compatible inputs
`Standard Military Drawing (SMD)
-'AC109: 5962-89551
-'ACT109: 5962-88534Pinout
SpecificationsSupply Voltage (VCC).........-0.5V to +7.0V
DC Input Diode Current (IIK)
VI = -0.5V ...................-20 mA
VI = VCC + 0.5V................ +20 mA
DC Input Voltage (VI) ..... .-0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = -0.5V................ ... 20 mA
VO = VCC + 0.5V................ +20 mA
DC Output Voltage (VO) ..... .-0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) ............. .±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) ..........±50 mA
Storage Temperature (TSTG) .... .-65°C to +150°C
Junction Temperature (TJ)
CDIP........................ 175°C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
| Temperature Min |
-55 deg C |
| Temperature Max |
125 deg C |
| View Using Catalog |
DescriptionThe 54AC109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to 54AC109 data sheet) by connecting the J and K inputs together.
54AC109 Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
The 54AC109 consists of two high-speed completely independent transition clocked JK# flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK# design allows operation as a D flip-flop (refer to 'AC/'ACT74 data sheet) by connecting the J and K# inputs together.
54AC109 Asynchronous Inputs:
LOW input to S#D (Set) sets Q to HIGH level
LOW input to C#D (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C#D and S#D makes both Q and Q#
HIGH
More Application Notes
| Title |
Size in Kbytes |
Date |
|
| AN-925: Radiation Design Test Data for Advanced CMOS Product |
194 Kbytes |
5-Aug-95 |
Download |
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|
54AC109 Data Sheet
