Features: `ICC reduced by 50%
`Ideal for addressable register applications
`Clock enable for address and data synchronization applications
`Eight edge-triggered D flip-flops
`Buffered common clock
`Outputs source/sink 24 mA
`See '273 for master reset version
`See '373 for transparent latch version
`See '374 for TRI-STATE® version
` 'ACT377 has TTL-compatible inputs
`Standard Microcircuit Drawing (SMD)
-'AC377: 5962-88702
-'ACT377: 5962-87697Pinout
SpecificationsIf Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC)........... −0.5V to +7.0V
DC Input Diode Current (IIK)
VI = −0.5V ................ ....−20 mA
VI = VCC + 0.5V.................. +20 mA
DC Input Voltage (VI) .........−0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
VO = −0.5V..................... −20 mA
VO = VCC + 0.5V.............. .... +20 mA
DC Output Voltage (VO) ........−0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) .................±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND) .............±50 mA
Storage Temperature (TSTG) .......−65°C to +150°C
Junction Temperature (TJ)
CDIP.......................... 175°C
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
Note 2: See individual datasheets for those devices which differ from the typical input rise and fall times noted here.
| Temperature Min |
-55 deg C |
| Temperature Max |
125 deg C |
| View Using Catalog |
DescriptionThe 54ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register 54ACT377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. TheCE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
The 54ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.
The register 54ACT377 is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
More Application Notes
| Title |
Size in Kbytes |
Date |
|
| AN-932: SEU and Latch Up Tolerant Advanced CMOS Technology |
186 Kbytes |
5-Jan-96 |
Download |
| AN-925: Radiation Design Test Data for Advanced CMOS Product |
194 Kbytes |
5-Aug-95 |
Download |
| AN-989: AN-989 Single Event Upset and Latchup Considerations for CMOS Devices Operated at 3.3 V |
91 Kbytes |
6-Oct-99 |
Download |
If you have trouble printing or viewing PDF file(s), see Printing Problems.
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54ACT377 Data Sheet
