MFG:N/A Package Cooled:CDIP D/C:N/A
MFG: N/A
Package Cooled: CDIP
D/C: N/A
Description: This device contains four independent gates, each of which performs the logic NAND function. The open-collector outputs require externa...
| Temperature Min | -55 deg C |
| Temperature Max | 125 deg C |
| View Using Catalog | |
54F38
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The 54F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.The register 54F377 is fully edge-triggered. The state ...
The 54F374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE#) are common to all flip-flops.
The 54F373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops 54F373 appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appea...
The 54F365 is a hex buffer and line driver designed to be employed as a memory and address driver, clock driver and bus-oriented transmitter/receiver.
The 54F322 is an 8-bit shift register with provision for either serial or parallel loading and with TRI-STATE. parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are ...
This 54F32 contains four independent gates, each of which performs the logic OR function.
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