54FCT

Features:

 ICC reduced to 40.0 mA
 Ideal buffer for MOS microprocessor or memory
 Eight edge-triggered D flip-flops
 Buffered common clock
 Buffered, asynchronous master reset
 TTL input and output level compatible
 TTL levels accept CMOS levels
 IOL e 48 mA (Com), 32 mA (Mil)
 NSC 54/74FCT273 is pin and functionally equivalent to IDT 54/74FCT273
 Military product compliant to MIL-STD-883 and Standard Military Drawing Ý5962-87656


Pinout




Specifications

Terminal Voltage with Respect to GND
    (VTERM)
    54FCT                                     -0.5 to a7.0V
    74FCT                                     -0.5 to a7.0V
Temperature Under Bias (TBIAS)
    74FCT                                 -55 to a125
    54FCT                                 -65 to a135
Storage Temperature (TSTG)
    74FCT                                 -55 to a125
54FCT b65§C to a150§C
DC Output Current (IOUT) 120 mA 


Description

The 54FCT has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

The register 54FCT is fully edge-triggered. The state of each D input,one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.