54HSCT630

The 54HSC/T630 is a 16-bit parallel Error Detection and Correction circuit. 54HSC/T630 uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word of 54HSC/T630 is stored with the data word during a memory write cycle. During a memory read cycle a 22-bit word is taken from memory and checked for errors.

Single bit errors of 54HSC/T630 in data words are flagged and corrected. Single bit errors in check words are flagged but not corrected. The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle.

Two bit errors of 54HSC/T630 are flagged but not corrected. Any combination of two bit errors occurring within the 22-bit word read from memory, (ie two errors in the 16-bit data word, two bits in the 16-bit check word or one error in each) will be correctly identified.

The gross errors of all bits, low or high about 54HSC/T630 , will be detected.

The control signals S1 and S0 of 54HSC/T630 select the function to be performed by the EDAC They control the generation of check words and the latching and correction of data (see table 1) When errors are detected, flags are placed on outputs SEF and DEF (see table 2).