56F8366

Features:

•Efficient 16-bit 56800E family controller engine with dual Harvard architecture
•Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
•Single-cycle 16 ×16-bit parallel Multiplier-Accumulator (MAC)
•Four 36-bit accumulators, including extension bits
•Arithmetic and logic multi-bit shifter
•Parallel instruction set with unique DSP addressing modes
•Hardware DO and REP loops
•Three internal address buses
•Four internal data buses
•Instruction set supports both DSP and controller functions
•Controller-style addressing modes and instructions for compact code
•Efficient C compiler and local variable support
•Software subroutine and interrupt stack with depth limited only by memory
•JTAG/EOnCE debug programming interface


Pinout




Description

The 56F8366 and 56F8166 are members of the 56800E core-based family of controllers. Each combines,on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8366 and 56F8166 are well-suited for many applications. The devices include many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control (56F8366 only), engine management, noise suppression, remote utility metering, industrial control for power,
lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code.The instruction set of 56F8366 is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.

The 56F8366 and 56F8166 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These 56F8366 alsoprovides two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines,depending on peripheral configuration.