5962-9951401QYA

The QPro™ series XQ1701L are Xilinx 3.3V high-density configuration PROMs. The XQR1701L are radiation hardened. These devices are manufactured on Xilinx QML certified manufacturing lines utilizing epitaxial substrates and TID lot qualification (per method 1019).

When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access  time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Figure 1 shows a simplied block diagram.

Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family.

For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers