5V19EE901NLGI

Specifications Package VFQFPN 32 Speed NA Temperature I Voltage 3.3 V Divide Input ...

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SeekIC No. : 004234775 Detail

5V19EE901NLGI: Specifications Package VFQFPN 32 Speed NA Temperature I Voltage 3.3 V ...

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Part Number:
5V19EE901NLGI
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/7

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Product Details

Description



Specifications

Package VFQFPN 32 Speed NA Temperature I Voltage 3.3 V Divide Input Input Frequency Jitter cycle-to-cycle Multiply No. of Inputs No. of Outputs Output Output Frequency Output Skew Type


Description

PROGRAMMABLE PLL AND VCXO
The 5V19EE901NLGI is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies of 5V19EE901NLGI are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic ormanual switchover function of 5V19EE901NLGI allows any one of the redundant clocks to be selected during normal operation.

The 5V19EE901NLGI is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up.

5V19EE901NLGI features:

  • Four internal PLLs
  • Internal non-volatile EEPROM
  • Fast (400kHz) mode I2C serial interface
  • Input frequency range: 1 MHz to 200 MHz
  • Output frequency range: 4.9 kHz to 500 MHz
  • Reference crystal input with programmable linear load capacitance
      Crystal frequency range: 8 MHz to 50 MHz (maximum crystal range is best effort)
  • Integrated VCXO
  • Each PLL has a 7-bit reference divider and a 12-bit feedback-divider
  • 8-bit output-divider blocks
  • Fractional division capability on one PLL
  • Two of the PLLs support spread spectrum generation capability
  • I/O Standards:
      Outputs - 3.3 V LVTTL/ LVCMOS
      Outputs - LVPECL, LVDS and HCSL
      Inputs - 3.3 V LVTTL/ LVCMOS
  • Programmable slew rate control
  • Programmable loop bandwidth
  • Programmable output inversion to reduce bimodal jitter
  • Redundant clock inputs with glitchless auto and manual switchover options
  • Individual output enable/disable
  • Power-down mode
  • 3.3V core VDD
  • Available in TSSOP and VFQFPN packages
  • -40 to +85°C Industrial Temp operation



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