5V60014DVGI8

Specifications

Temperature I Speed NA Voltage 3.3 V Package TSSOP 8 Divide Input Input Frequency Jitter cycle-to-cycle Max Prop Delay Multiply No. of Inputs No. of Outputs Max. Input Frequency Core Supply Voltage (VDD) Output Supply Voltage (VDDO) Output Output Frequency Output Skew Type Max. Output Frequency Output to Output Skew Device to Device Skew Multiplier/Divider Jitter Input Type Output Type


Description

ZDB
The 5V60014DVGI8 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. The 5V60014DVGI8 is designed to operate at low frequencies, with faster rise and fall times, and with lower phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both outputs, giving the appearance of no delay through the device. There are two outputs on the chip. The device has internal feedback loop eliminating the complexity of external feedback loop.The 5V60014DVGI8 is ideal for synchronizing outputs in a large variety of systems, from personal computers to datacommunications to video. The low phase noise performance makes the device particularly suitable for audio applications. By allowing off-chip feedback paths, the 5V60014DVGI8 can eliminate the delay through other devices.

5V60014DVGI8 features:

Packaged in 8-pin MSOP (Pb free)

Low phase noise zero delay buffer

Low skew outputs

Input clock frequency from 10 MHz to 38 MHz at 3.3 V

Phase noise of better than -100 dBc/Hz from 1 kHz to 1 MHz offset from carrier

Recover poor input clock duty cycle

Output clock duty cycle of 45/55 at 3.3 V

High drive strength

Full CMOS clock swings with 15 mA drive capability at TTL levels

Advanced, low power CMOS process

3.3 V operating voltages

Industrial Temperature Range: -40 to +85°C