6538

The 6538 is organized as a 65,536 x 16 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology.

The 6538 offers center power and ground pins for improved performance and noise immunity. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers chip enable (CE#), separate byte enable controls (BLE# and BHE#) and output enable (OE#) with this organization.

The 6538 offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements