72T20128L4BB

Specifications

Package PBGA 208 Speed 4 NS Temperature C Voltage 2.5 V Density 5 Mb Organization 256K x 20,512K x 10 Access Time 3.2 ns I/O Type 1.5 V HSTL,1.8 V HSTL,2.5 V LVTTL,3.3 V LVTTL Function JTAG,DDR/SDR,Bus Matching,Mark & Retransmit Family Name TeraSyncDDR Flags Empty/Full,Partial Full,Programmable,Partial Empty Bus Width x10/x20 Architecture Uni-directional Timing Type DDR Synchronous


Description

2.5V 256 X 20 DDR TERASYN
Double Data Rate Port Selectable, Bus Matching, 3.3/2.5/1.8/1.5-V port selectable I/O, Read Echo Outputs 72T20128L4BB