73M2910L

  The 73M2910L high performance micro-controller is based on the industry standard 8-bit 8032 implemented in an advanced submicron CMOS process. The processor has the attributes of the 8032, including instruction cycle time, UART, timers,interrupts, 256 bytes of on-chip RAM and programmable I/O. The architecture has been
optimized for low power portable modem or communication applications by integrating unique features with the core CPU.

  A key feature is a user friendly HDLC Packetizer,accessed through the special function registers. It has a serial I/O, hardware support for 16 and 32-bit CRC, zero insert/delete control, a dedicated interrupt and a clear channel mode for by-passing the packetizer.

   Other features of the 73M2910L include additional user programmable I/O with programmable bank select and chip select logic, designed to eliminate board level glue logic. It also includes two general-purpose input ports with programmable wakeup capability.

  For devices that require non-multiplexed address and data buses, eight latched outputs for the low byte of the address are available.

  The 73M2910L has two extra interrupt sources, an external interrupt and a HDLC interrupt. The HDLC interrupt has two registers associated with it; the HDLC Interrupt Register which is used to determine the source of the interrupt, and the HDLC Interrupt Enable Register that enables the source of the interrupt.

  The state of the external interrupts can be read through a register allowing the interrupt pins to be used as inputs. The interrupt pins INT0 and INT1 can be either negative edge, positive edge or level triggered. The INT2 pin is always edge triggered.

  Two buffered clock outputs have been added to support peripheral functions such as UARTs, modems and other clocked devices. The main internal processor clock frequency can be divided by 2 for power conservation in functional modes that only require half the clock speed.

   Additional internal special function registers of the 73M2910L are used for firmware control over the HDLC Packetizer,the clocks and the programmable I/O ports.

  To accommodate processor peripherals when operating at higher frequencies, the processor's timing has been altered to allow more address setup time for slower peripheral program ROM and memory mapped peripherals.

  For low power applications the 73M2910L supports two power conservation modes: idle and power-down. In the power-down state the total current consumption
is less than 10 µA at room temperature.