74ABTH16260

   The 74ABT16260/74ABTH16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path.Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface
applications. This device is alto useful in memory-interleaving applications.

   Three 12-bit I/O ports (A1A12, 1B11B12, and 2B12B12) are available for address and/or data transfer. The output enable (OE1B ,OE2B , and OEA ) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A to B direction.

   Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the latch enable input goes low, the data present at the inputs is latched and remains
latched until the latch enable input is returned high.

   To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.

   The 74ABTH incorporates the bus hold feature. The 74ABT does not include bus hold feature. Both parts are available in 56-pin SSOP and TSSOP.