74ACT16833

The 74ACT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY or 2PARITY is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.

The error (1ERR or 2ERR) output of the 74ACT16833 is configured as an open-collector output. The B-to-A parity error flag is clocked into 1ERR or 2ERR on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR or 2ERR is cleared (set high) by taking the clear (1CLR or 2CLR) input low.
 
The output-enable (OEA and OEB) inputs of the 74ACT16833 can be used to disable the device so that the buses are effectively isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic
capability.

The 74ACT16833 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.

The 74ACT16833 is characterized for operation over the full military temperature range of 55°C to 125°C. The 74ACT16833 is characterized for operation from 40°C to 85°C.