74ACT373

Features: ` HIGH SPEED: tPD = 6 ns (TYP.) atVCC = 5V` LOWPOWER DISSIPATION: ICC = 8 A (MAX.) at TA =25 oC` COMPATIBLEWITH TTLOUTPUTS VIH =2V(MIN), VIL = 0.8V (MAX)` 50 TRANSMISSIONLINE DRIVING CAPABILITY` SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL =24mA (MIN)` BALANCED PROPAGATIONDELAYS: tPLH= tPHL...

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74ACT373 Picture
SeekIC No. : 004249066 Detail

74ACT373: Features: ` HIGH SPEED: tPD = 6 ns (TYP.) atVCC = 5V` LOWPOWER DISSIPATION: ICC = 8 A (MAX.) at TA =25 oC` COMPATIBLEWITH TTLOUTPUTS VIH =2V(MIN), VIL = 0.8V (MAX)` 50 TRANSMISSIONLINE DRIVING CAPAB...

floor Price/Ceiling Price

Part Number:
74ACT373
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/3

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Product Details

Description



Features:

` HIGH SPEED: tPD = 6 ns (TYP.) atVCC = 5V
` LOWPOWER DISSIPATION:
    ICC = 8 A (MAX.) at TA =25 oC
` COMPATIBLEWITH TTLOUTPUTS
    VIH =2V(MIN), VIL = 0.8V (MAX)
` 50 TRANSMISSIONLINE DRIVING CAPABILITY
` SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = IOL =24mA (MIN)
` BALANCED PROPAGATIONDELAYS: tPLH = tPHL
` OPERATINGVOLTAGERANGE:
    VCC (OPR) = 4.5V to 5.5V
` PIN AND FUNCTION COMPATIBLEWITH
    74 SERIES 373
` IMPROVEDLATCH-UP IMMUNITY



Pinout

  Connection Diagram


Specifications

Symbol Parameter
Value
Unit
VCC Supply Voltage
-0.5 to +7
V
VI DC Input Voltage
-0.5 to VCC + 0.5
V
VO DC Output Voltage
-0.5 to VCC + 0.5
V
IIK DC Input Diode Current
± 20
mA
IOK DC Output Diode Current
± 20
mA
IO DC Output Current
± 20
mA
ICC or IGND DC VCC or Ground Current
± 400
mA
Tstg Storage Temperature
-65 to +150
TL Lead Temperature (10 sec)
300

AbsoluteMaximumRatings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.


Description

The 74ACT373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE).

While the LE inputs of the 74ACT373 is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components.

All inputs and outputs of the 74ACT373 are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.




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