74AHC132D

The 74AHC132D is a member of 74AHC/AHCT132 famili which are high-speed Si-gate CMOS devices and are pin compatible with low power schottky TTL (LSTTL). The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative VT- is defined as the hysteresis voltage VH. They are specified in compliance with JEDEC standard No. 7A.

The features of 74AHC132D can be summarized as (1)ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101; exceeds 1000 V; (2)balanced propagation delays; (3)inputs accepts voltages higher than VCC; (4)for AHC only: operates with CMOS input levels; (5)for AHCT only: operates with TTL input levels; (6)specified from -40 to +85 and +125 °C.

The absolute maximum ratings of 74AHC132D are (1)VCC DC voltage: -0.5/ +7.0 V; (2)VI input voltage range: 0.5/+7.0V; (3)IIK DC input diode current(VI < -0.5 V; note 1): 20 mA; (4)IOK DC output diode current(VO < -0.5 V or VO > VCC + 0.5 V; note 1): ±20mA; (5)IO DC output source or sink current(-0.5 V < VO < VCC + 0.5 V): ±25 mA; (6)ICC DC VCC or GND current: ±75mA; (7)Tstg storage temperature range: -65 to +150 °C; (8)PD power dissipation per package(for temperature range: -40 to +125 °C; note 2): 500mW(1. The input and output voltage ratings of the 74AHC132D may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K.)