74AHC573D

Latches OCTAL LATCH XVR W/DUAL ENABLE

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SeekIC No. : 00446139 Detail

74AHC573D: Latches OCTAL LATCH XVR W/DUAL ENABLE

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Part Number:
74AHC573D
Mfg:
NXP Semiconductors
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Quick Details

Number of Circuits : 8 Logic Type : CMOS
Logic Family : AHC Polarity : Non-Inverting
Number of Output Lines : 8 High Level Output Current : - 8 mA
Propagation Delay Time : 4.2 ns at 5 V Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 2 V Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 40 C Package / Case : SO-20
Packaging : Tube    

Description

Low Level Output Current :
Number of Circuits : 8
Maximum Operating Temperature : + 125 C
Minimum Operating Temperature : - 40 C
Polarity : Non-Inverting
High Level Output Current : - 8 mA
Supply Voltage - Max : 5.5 V
Supply Voltage - Min : 2 V
Number of Output Lines : 8
Packaging : Tube
Package / Case : SO-20
Logic Family : AHC
Logic Type : CMOS
Propagation Delay Time : 4.2 ns at 5 V


Description

The 74AHC573D belongs to 74AHC/AHCT573 family which are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. They are specified in compliance with JEDEC standard No. 7A. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches. When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs of the 74AHC573D go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The '573' consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. The '573' is functionally identical to the '533', '563' and '373', but the '533' and '563' have inverted outputs and the '563' and '373' have a different pin arrangement.

The features of 74AHC573D can be summarized as (1)ESD protection: HBM EIA/JESD22-A114-A, exceeds 2000 V, MM EIA/JESD22-A115-A, exceeds 200 V, CDM EIA/JESD22-C101, exceeds 1000 V; (2)balanced propagation delays; (3)all inputs have schmitt-trigger actions; (4)common 3-state output enable input; (5)functionally identical to the '563' and '373'; (6)inputs accepts voltages higher than VCC; (7)for AHC only: operates with CMOS input levels; (8)for AHCT only: operates with TTL input levels; (9)specified from -40 to +85 and +125 °C.

The absolute maximum ratings of 74AHC573D are (1)VCC DC supply voltage: -0.5 to +7.0V; (2)VI input voltage range: -0.5 to +7.0V; (3)IIK DC input diode current(VI < -0.5 V; note 1): -20mA; (4)IOK DC output diode current(VO < -0.5 V or VO > VCC + 0.5 V; note 1): ±20mA; (5)IO DC output source or sink current (-0.5 V < VO < VCC + 0.5 V): ±25mA; (6)ICC DC VCC or GND current: ±75mA; (7)Tstg storage temperature range: -65 to +150 °C; (8)PD power dissipation per package(for temperature range: -40 to +125 °C; note 2): 500mW.




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