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Part Number: 74AHCT377
Description: The 74AHC/AHCT377 D-type flip-flops are high-speed silicon-gate CMOS devices and are pin compatible wi...
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74AHCT377
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General Description
74AHCT377 General Description
The 74AHC/AHCT377 D-type flip-flops are high-speed silicon-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.
The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.
74AHCT377 Maximum Ratings
| SYMBOL | PARAMETER | CONDITIONS | MIN | MAX | UNIT |
| VCC | DC supply voltage | +7.0 | V | ||
| VI | supply voltage | -0.5 | +7.0 | V | |
| IIK | input diode current | VI < -0.5 V; note 1 | -0.5 | -20 | mA |
| ISK | switch diode current | VO < -0.5 V or VO > VCC + 0.5 V; note 1 | - | ±20 | mA |
| IS | switch source or sink current | -0.5 V < VO < VCC + 0.5 V | - | ±25 | mA |
| ICC, IGND | VCC or GND current | - | ±75 | mA | |
| Tstg | storage temperature | -65 | +150 | °C | |
| PD | power dissipation per package | for temperature range: -40 to +125 °C; note 2 | - | 500 | mW |
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K.
74AHCT377 Features
` ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
` Balanced propagation delays
` All inputs have Schmitt-trigger actions
` Inputs accept voltages higher than VCC
` Ideal for addressable register applications
` Data enable for address and data synchronization
` Eight positive-edge triggered D-type flip-flops
` See "273" for master reset version
` See "373" for transparent latch version
` See "374" for 3-state version
` For AHC only: operates with CMOS input levels
` For AHCT only: operates with TTL input levels
` Specified from -40 to +85 and from -40 to +125 °C.
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
` Balanced propagation delays
` All inputs have Schmitt-trigger actions
` Inputs accept voltages higher than VCC
` Ideal for addressable register applications
` Data enable for address and data synchronization
` Eight positive-edge triggered D-type flip-flops
` See "273" for master reset version
` See "373" for transparent latch version
` See "374" for 3-state version
` For AHC only: operates with CMOS input levels
` For AHCT only: operates with TTL input levels
` Specified from -40 to +85 and from -40 to +125 °C.
74AHCT377 Connection Diagram
74AHCT377
PDF/DataSheet Download
- Datasheet: 74AHCT377
- File Size: 103917 KB
- Manufacturer: Philips
- Click here to Download
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74AHCT377 Relative Products
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The 74AHCT374 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No.7A. The 74AHCT374 are octal D-type flip-flops featuring separate D-type inputs for each fli...
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