74ALVC16240 General Description
The ALVC16240 contains sixteen inverting buffers with 3- STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble (4-bit) controlled. Each nibble has sep- arate 3-STATE control inputs which can be shorted together for full 16-bit operation.
The 74ALVC16240 is designed for low voltage (1.65V to 3.6V) V applications with I/O capability up to 3.6V.CC The 74ALVC16240 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
74ALVC16240 Maximum Ratings
Supply Voltage (V ) .................................0.5V to 4.6VCC
DC Input Voltage (V).................................. 0.5V to 4.6VI
Output Voltage (V ) (Note 3)....- 0.5V to V + 0.5V O - CC
DC Input Diode Current (I ) .................IK V 0V 50 mA I
DC Output Diode Current (I ) OK V ............ 0V 50 mA O
DC Output Source/Sink Current (I /I )........ 50 mA OH OL
DC V or GND Current per CC
Supply Pin (I or GND).................................... 100 mA CC
Storage Temperature Range (TSTG). -65°C to +150°C
74ALVC16240 Features
1.65V to 3.6V V supply operation
CC 3.6V tolerant inputs and outputs
t PD
3.0 ns max for 3.0V to 3.6V VCC
3.5 ns max for 2.3V to 2.7V V CC
6.0 ns max for 1.65V to 1.95V VCC
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Uses patented noise/EMI reduction circuitry
Latchup conforms to JEDEC JED78
ESD performance:
Human body model > 2000V
Machine model > 200V
74ALVC16240 Connection Diagram
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