74ALVCH16500

The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE_AB and OE_BA), latch enable (LE_AB and LE_BA), and clock (CP_AB and CP_BA) inputs. For A-to-B data flow, the 74ALVCH16500 operates in the transparent mode when LE_AB is High. When LEAB is Low, the A data is latched if CP_AB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CP_AB. When OE_AB is High, the outputs are active. When OE_AB is Low, the outputs are in the high-impedance state.

Data of the 74ALVCH16500 flow for B-to-A is similar to that of A-to-B but uses OE_BA, LE_BA and CP_BA. The output enables are  omplimentary (OE_AB is active High, and OE_BA is active Low).

To ensure the high impedance state of the 74ALVCH16500 during power up or power down, OE_BA should be tied to VCC through a pullup resistor and OE_AB should be tied to GND through a pulldown resistor; the minimum value of the resistor is etermined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry of the 74ALVCH16500 is provided to hold unused or floating data inputs at a valid logic level.