74ALVCH16543

Features:

· In accordance with JEDEC standard no 8-1A
· CMOS low power consumption
· Direct interface with TTL levels
· MULTIBYTEä flow-through pin-out architecture
· 16-bit transceiver with D-type latch
· Combines 16245 and 16373 type functions in one chip
· Back-to-back registers for storage
· Output drive capability 50 W transmission lines at 85 °C
· Separate controls for data flow in each direction
· All data inputs have bus hold
· 3-state non-inverting outputs for bus oriented applications
· Current drive ±24 mA at 3.0 V.


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	DC supply voltage		0.5	+4.6	V
IIK	DC input diode current	VI < 0	-	-50	mA
VI	DC input voltage	note 1		+4.6	V
IOK	DC output diode current	VO > VCC or VO < 0	0.5	±50	mA
VO	DC output voltage	note 1		VCC + 0.5	V
IO	DC output source or sink current	VO = 0 to VCC		±50	mA
ICC, IGND	DC VCC or GND current		65	±100	mA
Tstg	storage temperature			+150	°C
Ptot	power dissipation	for temperature range: -40 to +125 °C; note 2	-	600	mW

Description

The 74ALVCH16543 is a dual octal registered transceiver.Each section contains two sets of D-type latches for temporary storage of the data flow in either direction.

Separate latch enable (n LE_AB, n LE_BA) and output of the 74ALVCH16543 enable (n OE_AB, n OE_BA) inputs are provided for each register to permit independent control in either direction of the data flow.