74ALVCH16601

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE_AB and OE_BA), latch enable (LEAB and LEBA), and clock (CP_AB and CP_BA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LE_AB is Low, the A data is latched if CP_AB is held at a High or Low logic level. If LEABis Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OE_AB is Low, the outputs are active. When OE_AB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs
(CE_BA/CE_AB).

Data of the 74ALVCH16601 flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state of the 74ALVCH16601 during power up or power down, OE_BA and OE_AB should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry of the 74ALVCH16601 is provided to hold unused or floating data inputs at a valid logic level.