Features: ` Wide supply voltage range from 0.8 to 2.7 V` Performance optimised for VCC = 1.8 V` High noise immunity` Complies with JEDEC standard: JESD76 (1.65 to 1.95 V)` 8 mA output drive (VCC = 1.65 V)` CMOS low power consumption` Latch-up performance £250 mA` 3.3 V tolerant inputs/outpu...
74AUC1G32: Features: ` Wide supply voltage range from 0.8 to 2.7 V` Performance optimised for VCC = 1.8 V` High noise immunity` Complies with JEDEC standard: JESD76 (1.65 to 1.95 V)` 8 mA output drive (VCC = ...
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| SYMBOL | PARAMETER | CONDITIONS | MIN. | MAX. | UNIT |
| VCC | supply voltage | -0.5 | +3.6 | V | |
| IIK | input diode current | VI < 0 | - | -50 | mA |
| VI | input voltage | note 1 | -0.5 | +3.6 | V |
| IOK | output diode current | VO > VCC or VO < 0 | - | ±50 | mA |
| VO | output voltage | active mode; notes 1 and 2 | -0.5 | VCC + 0.5 | V |
| Power-down mode; notes 1 and 2 | -0.5 | +3.6 | V | ||
| IO | output sink current | VO = 0 to VCC | - | ±60 | mA |
| ICC, IGND | VCC or GND current | - | ±100 | mA | |
| Tstg | storage temperature | -65 | +150 | °C | |
| PD | power dissipation | for temperature range from -40 to +85 °C |
- | 250 | mW |
The 74AUC1G32 is a high-performance, low-power, low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
The 74AUC1G32 is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging current backflow through the device when it is powered down.
The 74AUC1G32 provides the single 2-input OR function.