Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1.8 V to 2.7 V)`JESD8-B (2.7 V to 3.6 V)`ESD protection:`HBM JESD22-A114-D Class 3A exceeds 5000 V`MM ...
74AUP1G06: Features: `Wide supply voltage range from 0.8 V to 3.6 V`High noise immunity`Complies with JEDEC standards:`JESD8-12 (0.8 V to 1.3 V)`JESD8-11 (0.9 V to 1.65 V)`JESD8-7 (1.2 V to 1.95 V)`JESD8-5 (1....
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

The 74AUP1G06 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
The 74AUP1G06 ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G06 provides the single inverting buffer with open-drain output.
The output of the 74AUP1G06 is an open drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.