74AUP1T45

[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are  bserved.
[2] The values of V_CC(A) and V_CC(B) are provided in the recommended operating conditions; see Table 6.
[3] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.

The 74AUP1T45 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (V_CC(A) and V_CC(B)) which enable bidirectional level translation. Both V_CC(A) and V_CC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to V_CC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

Schmitt trigger action of the 74AUP1T45 on all inputs makes the circuit tolerant of slower input rise and fall times across the entire V_CC(A) and V_CC(B) ranges. The device ensures low static and dynamic power consumption and is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the 74AUP1T45 then it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND, both A and B are in the high-impedance OFF-state.