Features: ` Wide supply voltage range from 0.8 V to 3.6 V` High noise immunity` Complies with JEDEC standards:` JESD8-12 (0.8 V to 1.3 V)` JESD8-11 (0.9 V to 1.65 V)` JESD8-7 (1.2 V to 1.95 V)` JESD8-5 (1.8 V to 2.7 V)` JESD8-B (2.7 V to 3.6 V)` ESD protection:` HBM JESD22-A114E Class 3A exceeds 5...
74AUP2G17: Features: ` Wide supply voltage range from 0.8 V to 3.6 V` High noise immunity` Complies with JEDEC standards:` JESD8-12 (0.8 V to 1.3 V)` JESD8-11 (0.9 V to 1.65 V)` JESD8-7 (1.2 V to 1.95 V)` JESD...
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|
Symbol |
Parameter |
Conditions |
Min. |
Max. |
Unit |
|
VCC |
supply voltage |
-0.5 |
+4.6 |
V | |
|
IIK |
input clamping current | VI < 0 V |
- |
-50 |
mA |
|
VI |
input voltage |
-0.5 |
+4.6 |
V | |
|
IOK |
output clamping current | VO > VCC or VO < 0 V |
- |
±50 |
mA |
|
VO |
output voltage | Active mode and Power-down mode |
-0.5 |
+4.6 |
V |
|
IO |
output current | VO = 0 V to VCC |
- |
±20 |
mA |
|
ICC |
supply current |
- |
50 |
mA | |
|
IGND |
ground current |
- |
-50 |
mA | |
|
Tstg |
storage temperature |
-65 |
+150 |
||
|
Ptot |
total power dissipation | Tamb = -40 to +125 |
- |
250 |
mW |
The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device,superior to most advanced CMOS compatible TTL families.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry of the 74AUP2G17 disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.